Verilog Initial Block Value of 3-bit reg ignored by Quartus 14.0 synthesis

Altera_Forum · ‎08-17-2014

Hi,

I am using a Verilog initial block to power-up certain reg's to high. My code looks something like this:

reg a;

reg[1:0] b;

reg[2:0] c;

initial begin

a = 1'b0;

b = 2'b11;

c = 3'b111;

end

When I compile the design to run on Stratix V, Quartus synthesis is honoring the initial low value on 'a' and high value on 'b', but is powering up 'c' to zero (3'b000). There is no warning message saying the synthesizer could not honor the power-up high value supplied in the Verilog code.

Could there be any valid reason why Quartus would completely ignore the initial assignment to 'c'? Alternatively, could it be a bug in Quartus?

Thank you

Altera_Forum · ‎08-17-2014

I believe I figured this out. Quartus inferred that 'c' was a state machine having a reset value of 0, so powered up 'c' to 0 without alerting me of having synthesized away the initial assignment from the Verilog code. Quartus optimizations can be dangerous when they change the logic from the HDL code.

Altera_Forum · ‎08-17-2014

If it made it into a state machine, it will have changed the encoding of the states, hence the reset to 0. The default is to encode the states as 1-hot.