expecting a description

Altera_Forum · ‎08-13-2014

Hi,

what is the meaning (and reason) of syntax error:

10170 Verilog HDL syntax error at lights.v(6) near text ";"; expecting a description

(line 6 is the "endmodule"; using 13.01 Quartus; I am using a sample code from a book;

as far as I could check, the syntax is correct)

Thanks in advance


module clk_gen;
    reg clk;
    initial clk = 1'b0;
    always# 10 clk = ~clk;
    initial# 60 $finish;
endmodule;

Altera_Forum · ‎08-13-2014

endmodule should not have a semicolon (;) at the end

Altera_Forum · ‎08-14-2014

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endmodule should not have a semicolon (;) at the end

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Thank you, really. (BTW: I think an empty instruction should be tolerated, and the error message could be more informative).

I have, however, more problems.

About line, containing '$finish', the compiler gives the warning "ignoring unsupported system task".

(As far as I know, $finish should be supported)

The bigger problem is the error the compiler reports:

"Can't synthetise current design -- Top partition does not contain any logic"

Which is absolutlely true. But, I did not want to synthetise, just to simulate and show the waveform.

Is there any setting that allows to to that?

And in general, shall I change some setting to compile ONLY for simulation?

Altera_Forum · ‎08-15-2014

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Thank you, really. (BTW: I think an empty instruction should be tolerated, and the error message could be more informative).

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FYI, moving to SystemVerilog will allow the null statement.