Verilog SD card controller in 4 bit mode

[Altera_Forum]

I'm trying to use 4 bit mode to write to my SD card to have very high throughput. If found an open source verilog controller on opencores.org (http://opencores.org/project,sdcard_mass_storage_controller) 

However, this core was written for a wishbone bus and was tested on an Actel FPGA. I modified an Wishbone - AVMM wrapper to interface this core with qsys and the avalon bus. (original thread: http://www.alteraforum.com/forum/showthread.php?t=2238)  Qsys had no errors generating interconnects. Now I'm in quartus trying to synthesize the design. I am getting a host of errors: Error (10200): Verilog HDL Conditional Statement error at sd_controller_wb.v(280): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct Error (10818): Can't infer register for "cmd_int_busy" at sd_controller_wb.v(177) because it does not hold its value outside the clock edge etc.  These look like serious verilog errors. I am wondering how come the original creator of this code was able to synthesize the design without errors and verify its functionality. He of course synthesized this for Actel, but I believe the verilog code in this project is generic. I've been trying to clean up the code by hand but it is very difficult.  Also, if anyone has used the SD card in 4 bit mode via verilog or vhdl, can they post some code?  Thanks.  Interestingly, Lattice Semi uses this code for their SD controller, but they are wishbone complaint: http://www.latticesemi.com/~/media/documents/referencedesigns/sz/sdflashcontrollerusingsdbus-documentation.pdf?document_id=36706

[Altera_Forum]

--- Quote Start ---  I'm trying to use 4 bit mode to write to my SD card to have very high throughput. If found an open source verilog controller on opencores.org (http://opencores.org/project,sdcard_mass_storage_controller) However, this core was written for a wishbone bus and was tested on an Actel FPGA. I modified an Wishbone - AVMM wrapper to interface this core with qsys and the avalon bus. (original thread: http://www.alteraforum.com/forum/showthread.php?t=2238)  Qsys had no errors generating interconnects. Now I'm in quartus trying to synthesize the design. I am getting a host of errors: Error (10200): Verilog HDL Conditional Statement error at sd_controller_wb.v(280): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct Error (10818): Can't infer register for "cmd_int_busy" at sd_controller_wb.v(177) because it does not hold its value outside the clock edge etc.  These look like serious verilog errors. I am wondering how come the original creator of this code was able to synthesize the design without errors and verify its functionality. He of course synthesized this for Actel, but I believe the verilog code in this project is generic. I've been trying to clean up the code by hand but it is very difficult.  Also, if anyone has used the SD card in 4 bit mode via verilog or vhdl, can they post some code?  Thanks.  Interestingly, Lattice Semi uses this code for their SD controller, but they are wishbone complaint: http://www.latticesemi.com/~/media/documents/referencedesigns/sz/sdflashcontrollerusingsdbus-documentation.pdf?document_id=36706  --- Quote End ---     Do you solve the problem,i also encountered this problem. If you worked out,would you share with me?thank you

[Altera_Forum]

could you please paste the code. So I can help.