Hello guys,
a part of my project requires creating a main memory of 4GB M[0..2^32-1]<7..0>
you have the following signals:
DataIn<31..0>
DataOut<31..0>
Address<31..0>
read
write
if (read) then M[address]<31..0>=dataIn<31..0>
if (write) then dataOut <31..0>= M[address]<31..0>
the problem is i don't know how to use verilog!!
i know how to implement this and how it works i know by choosing a specific address i'm going to output:
dataPut = M[address]#M[address+1]#M[address+2]#M[address+3]
and the same for input, data in will be divided to 4 parts saved in 4 consecutive memory addresses starting at "address".
please i need help in how to write this in verilog, the dr advised searching the internet but i didn't find what i was looking for though there's alot of codes available maybe what i need is there but the fact that i don't get verilog is the problem!
first i thought i'd implement a 1GB which takes 8 bits and outputs 8 bits, and the 32 bit data will be divided to each one of these 4 1GB and specified by one address but it seems a bit too much and the address line will need then 30 bits instead of 32 but hey i can leave it at 32 right? or at least i think i can!
please advise on how to do verilog for such a memory and thanks in advance.. sorry for the long story but this thing is stressing me out..
