Hello all, I am trying to build a design containing hierarchical verilog paths in Quartus, for example: wire usr_led = foo.bar.signalname; but Quartus gives me: Error (10207): Verilog HDL error at module.v(650): can't resolve reference to object "signalname". According to the quartus manual, "Hierarchical Names Supported. No references to objects outside the current module." I could port the signals to the top level, but this is for debugging only, and I don't want to disturb the underlying code (and need to undo my changes after I'm done testing). Has anyone else gotten this to work? I've double checked my module paths and signal names, and everything looks correct.
