Verilog hierarchical path names in Quartus

[Altera_Forum]

Hello all, I am trying to build a design containing hierarchical verilog paths in Quartus, for example: wire usr_led = foo.bar.signalname; but Quartus gives me: Error (10207): Verilog HDL error at module.v(650): can't resolve reference to object "signalname". According to the quartus manual, "Hierarchical Names Supported. No references to objects outside the current module." I could port the signals to the top level, but this is for debugging only, and I don't want to disturb the underlying code (and need to undo my changes after I'm done testing). Has anyone else gotten this to work? I've double checked my module paths and signal names, and everything looks correct.

[Altera_Forum]

Can the experts please reply? thanks.

[Altera_Forum]

I did not think this was possible, and from your test it doesn't seem to work, but would be very happy if it did. (This could be very confusing if used incorrectly, but debug is a perfect case...) If nobody responds, please file an SR and let us know the result?

[Altera_Forum]

Hi, 

 do you want to observe the signal only in your simulation or do you want to see the signal in realtime ?  Kind regards  GPK

[Altera_Forum]

is this really not supported? how does signaltap connect to signals then?

[Altera_Forum]

SignalTap is not done in HDL, but instead has its own GUI and "hidden infrastructure". So yes, it does probe signals without having to hook up to them directly, but it can't be used for general logic. Does anyone know of other synthesis tools that support hierarchical names? Just curious.

[Altera_Forum]

questasim and whatever is used for mentor's veloce do support hierarchical names.

[Altera_Forum]

I believe those are both simulation tools(not sure about the second). Modelsim also supports it. It's extremely useful in simulation, since you can bring out signals for watching and analyzing very quickly. I would be surprised if any major simulations tools didn't support it, but I'm curious about synthesis tools.

[Altera_Forum]

The veloce one is actually a synthesis tool, is used for emulation. Do you know if there's a way to route back signals from signaltap to the design?

[Altera_Forum]

SignalTap is purely for capturing data. In System Signals and Probes can be used to easily drive signals via JTAG, but it does need to be hooked into your design.