Verilog porting woes

Altera_Forum · ‎06-16-2012

I'm a VHDL guy trying to port some verilog to a cyclone3.

The unmodified verilog source produces parse type errors when quartus attempts to compile it.

The thing that has me confused is that company X's software compiles this without problem. I'm thinking that there must be some language feature that is throwing quartus off. Not being a Verilog expert I'm a little unsure of how to proceed.

I've also tried all three settings for Verilog version in the analysis and synthesis settings.

Does anyone have ideas of how to get this to compile?

Thanks,

-marty

Here is the source file "sha256_pipes2.v":


/*!
   btcminer -- BTCMiner for ZTEX USB-FPGA Modules: HDL code: hash pipelines
   Copyright (C) 2011 ZTEX GmbH
   <no links here>
   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License version 3 as
   published by the Free Software Foundation.
   This program is distributed in the hope that it will be useful, but
   WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
   General Public License for more details.
   You should have received a copy of the GNU General Public License
   along with this program; if not, see <no links here>.
!*/
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
`define E0(x) ( {{x},{x}} ^ {{x},{x}} ^ {{x},{x}} )
`define E1(x) ( {{x},{x}} ^ {{x},{x}} ^ {{x},{x}} )
`define CH(x,y,z) ( (z) ^ ((x) & ((y) ^ (z))) )
`define MAJ(x,y,z) ( ((x) & (y)) | ((z) & ((x) | (y))) )
`define S0(x) ( { {x} ^ {x}, {{x}, {x}} ^ {{x},{x}} ^ {x} } )
`define S1(x) ( { {x} ^ {x}, {{x}, {x}} ^ {{x},{x}} ^ {x} } )
module sha256_pipe2_base ( clk, i_state, i_data, out );
    parameter STAGES = 64;
    
    input clk;
    input  i_state;
    input  i_data;
    output  out;
    localparam Ks = {
        32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
        32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
        32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
        32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
        32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
        32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
        32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
        32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
        32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
        32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
        32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
        32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
        32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
        32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
        32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
        32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2 
    };
    genvar i;
    
    generate
        for (i = 0; i <= STAGES; i = i + 1) begin : S
        reg  data;
        reg  state;
        reg  t1_p1;
        if(i == 0) 
        begin
            reg  o_state;
            
            always @ (posedge clk)
            begin
            data <= i_data;
            state <= i_state;
            t1_p1 <= i_state + i_data + Ks;
            end
            
        end else
        begin
        
            reg  data_buf;
            reg  state_buf;
            reg  data15_p1, data15_p2, data15_p3, t1;
            always @ (posedge clk)
            begin
            data_buf <= S.data;
            data <= data_buf;
            data15_p1 <= `S1( S.data );                                          // 3
            data15_p2 <= data15_p1;                                                     // 1
            data15_p3 <= ( ( i == 1 ) ? `S1( S.data ) : S.data15_p2 ) + S.data + S.data;    // 3
            data <= `S0( data_buf ) + data15_p3;                                     // 4
            
            state_buf <= S.state;                                                  // 2
            
            t1 <= `CH( S.state, S.state, S.state ) + `E1( S.state ) + S.t1_p1; // 6
            state <= `MAJ( state_buf, state_buf, state_buf ) + `E0( state_buf ) + t1;      // 7
            state <= state_buf;                                               // 1
            state <= state_buf;                                               // 1
            state <= state_buf;                                               // 1
            state <= state_buf + t1;                                          // 2
            state <= state_buf;                                               // 1
            state <= state_buf;                                               // 1
            t1_p1 <= state_buf + data_buf + Ks;                           // 2
            end
        end
        end
    endgenerate
    reg  state7, state7_buf;
    always @ (posedge clk)
    begin
        state7_buf <= S.state;
        state7 <= state7_buf;
    end
    assign out = S.state;
    assign out = state7;
endmodule

Here is the compile log:

Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition
    Info: Processing started: Sat Jun 16 06:38:26 2012
    Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition
    Info: Processing started: Sat Jun 16 06:38:26 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off c3_miner_usb -c fpgaminer_top
Warning: Parallel compilation is not licensed and has been disabled
Error (10170): Verilog HDL syntax error at sha256_pipes2.v(89) near text "[";  expecting "}"
Error (10170): Verilog HDL syntax error at sha256_pipes2.v(89) near text "[";  expecting "<=", or "="
Error (10170): Verilog HDL syntax error at sha256_pipes2.v(91) near text "[";  expecting "}"
Error (10170): Verilog HDL syntax error at sha256_pipes2.v(91) near text "[";  expecting "<=", or "="
Error (10170): Verilog HDL syntax error at sha256_pipes2.v(91) near text ")";  expecting "<=", or "="
Error (10170): Verilog HDL syntax error at sha256_pipes2.v(91) near text "+";  expecting "<=", or "="
Error (10170): Verilog HDL syntax error at sha256_pipes2.v(91) near text ";";  expecting "<=", or "="
Error (10170): Verilog HDL syntax error at sha256_pipes2.v(92) near text "[";  expecting "}"
Error (10170): Verilog HDL syntax error at sha256_pipes2.v(92) near text "[";  expecting "<=", or "="
Error (10170): Verilog HDL syntax error at sha256_pipes2.v(96) near text "[";  expecting "}"
Error (10170): Verilog HDL syntax error at sha256_pipes2.v(98) near text "[";  expecting "}"
Error (10112): Ignored design unit "sha256_pipe2_base" at sha256_pipes2.v(27) due to previous errors

Altera_Forum · ‎06-16-2012

It seems like Quartus Verilog doesn't like a particular construct in the macros.

It doesn't understand the part selects like {x}[16:7]. define S1(x) ( { {x} ^ {x}, {{x}, {x}} ^ {{x},{x}} ^ {x} } )

It should be possible to change the macros to use a different part select syntax, but hardly without some basic Verilog knowledge.

Altera_Forum · ‎06-16-2012

I think the problem is the use of "{x}[16:7]" instead of just "x[16:9]".

I have no idea why it does so. As far as I know, the meaning is the same.

Altera_Forum · ‎06-17-2012

After macro evaluation, you get expressions like S[i-1].data[511:480][6:0] that aren't accepted by Quartus. You need to change the macro to procuce S[i-1].data[486:480] instead.