Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
17258 Discussions

Verilog reviewing

Altera_Forum
Honored Contributor II
‎07-06-2010 03:15 PM
1,206 Views

Hello, 

 

I'd like to know if somebody's heard about Verilog reviewing script. Actually, I made many IPs and I reviewed all of them by myself to delete redundancies. For example, when a signal is set to '1' in a state machine and when this signal is always '1' previous to the assertion, it is a redundancy. 

 

Does somebody know a script or methods to detect this redundancy ? 

 

Best regards, 

 

Julien.
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎07-06-2010 03:28 PM
539 Views

I've never used any of them, but there seem to be a number of "lint" tools for Verilog/VHDL. 

http://www.asic-world.com/verilog/tools.html
0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.