Verilog

[VerLearn]

I have a question where I need to stay for certain amount of time looping in the code. I'm facing the problem of applying the clock to the circuit. Example: module ................ ................ always@(posedge clk) begin case() s0: begin ................... for(i=0;i<100;i=i+1) begin .................. .................. end s0: begin ................... for(i=0;i<20;i=i+1) begin .................. .................. end s0: begin ................... for(i=0;i<100;i=i+1) begin .................. .................. end s0: begin ................... for(i=0;i<20;i=i+1) begin .................. .................. end endcase end endmodule For the above circuit, how do I provide synchronous clock? 1. I should execute my first loop for exactly 100 times and display the output. 2. I should execute my second loop for exactly 20 times and display the output. 3. I should execute my third loop for exactly 100 times and display the output. 4. I should execute my fourth loop for exactly 20 times and display the output. Please help, thanks in advance.

[VerLearn]

Case parameters must be s0,s1,s2,s3. I unfortunately used s0 everywhere.

[Sebastian_M_Intel]

Hello VerLearn, 

Thank you for posting on the Intel® communities. 

We would like to inform you that we have a forum for these specific issues and products, so we are moving it to the "Intel® Quartus® Prime Software" subforum so you can get better support for this matter. 

https://community.intel.com/t5/Intel-Quartus-Prime-Software/bd-p/quartus-prime-software  

Best regards, 

Sebastian M 

Intel Customer Support Technician

[sstrell]

You're thinking like a software engineer and not a hardware designer.  For an FPGA design, you want to create counter hardware that counts up to what you want (a modulus counter) and then can send a signal out that indicates that count is complete and perhaps use the same output signal to start the next counter.  A modulus 100 counter for this could look like:

module count 
	#(parameter modulus = 100)
	(
	input clock, aclr_n,
	output reg [7:0] q = 0
);

reg count100complete;

always @(posedge clock, negedge aclr_n) 
begin
	if (aclr_n == 0) begin
		q[7:0] <= 0;
                count100complete <= 1'b0;
        end
	else begin
		if (q == modulus - 1) begin
			q <= 8’d0;
                        count100complete <= 1'b1;
                end
		else
			q <= q + 1;
	end
end
endmodule

Then you could do an if check on count100complete in another always block that starts the next counter if you're chaining them together and as an indicator that 100 cycles of whatever you are trying to perform is complete.

If you do need to make use of the incrementing index value and not just for timing a certain number of cycles, you could incorporate for loops as you've mentioned separate from this counter logic.