Verliog - & and | operations backwards?

[Altera_Forum]

I am learning Verilog and at a stage in which I would like to see some results from my dev board. 

I have started with a very simple program which takes two inputs and uses the "&" function to output the result to an LED. When running the program I noticed something was not right, I was getting the "or" function instead of an "and" function. After much dabbling I decided to try the "or" function instead, and to my surprise it was outputting the "and" function. I am not sure if I am doing something wrong or I have found a bug but I am most perplexed. The Quartus version I am running is 13.0s1 web edition and below is my code that I am running.  module Test ( input in_1, input in_2, input clk, output reg out_1 ); always @ (posedge clk) begin out_1 = (in_1 & in_2); end endmodule  Any help is much appreciated!

[Altera_Forum]

Check to see if the LEDs are active low. Thats usually the problem

[Altera_Forum]

--- Quote Start ---  Check to see if the LEDs are active low. Thats usually the problem  --- Quote End ---    Thank you for the reply. The problem that I am having is that when I use the "&" operator the truth table that I get is for an "or" gate and vice versa when I use the "|" operator. (also my LED is active when it has a high input)

[Altera_Forum]

What is the dev. board you have?

[Altera_Forum]

One thing I noticed is that you are using posedge clk but you are using blocking assignment. Did you supply clock to your module? 

 You can try: always @ (in_1, in_2)  begin  out_1 = (in_1 & in_2);  end  or if you have a clock supplied: always @ (posedge clk)  begin  out_1 <= (in_1 & in_2);  end

[Altera_Forum]

--- Quote Start ---  Thank you for the reply. The problem that I am having is that when I use the "&" operator the truth table that I get is for an "or" gate and vice versa when I use the "|" operator. (also my LED is active when it has a high input)  --- Quote End ---   Are you absolutely sure about that? Because from what you describe it seems that both your inputs and outputs are active low. In your example code, if you assume that in_1 and in_2 are normally '1' and they become '0' when you press the key, then your out_1 will be normally '1' and become '0' if one or both of the two keys is pressed. Therefore if the LED is also active low, it will light when one or both of the keys is pressed, implementing what looks like an 'or' function, even if you used the '&' operator.  Remember that an AND gate with all its inputs and outputs inverted is an OR gate (and vice versa)

[Altera_Forum]

--- Quote Start ---  What is the dev. board you have?  --- Quote End ---    Thanks for the reply. The board I am using is this http://www.21eda.net/product_184.html (sorry its in chincese :/)

[Altera_Forum]

--- Quote Start ---  One thing I noticed is that you are using posedge clk but you are using blocking assignment. Did you supply clock to your module?  You can try: always @ (in_1, in_2)  begin  out_1 = (in_1 & in_2);  end  or if you have a clock supplied: always @ (posedge clk)  begin  out_1 <= (in_1 & in_2);  end  --- Quote End ---    Thank you for you reply. I am using an on board clock running at 50Mhz.

[Altera_Forum]

--- Quote Start ---  Are you absolutely sure about that? Because from what you describe it seems that both your inputs and outputs are active low. In your example code, if you assume that in_1 and in_2 are normally '1' and they become '0' when you press the key, then your out_1 will be normally '1' and become '0' if one or both of the two keys is pressed. Therefore if the LED is also active low, it will light when one or both of the keys is pressed, implementing what looks like an 'or' function, even if you used the '&' operator.  Remember that an AND gate with all its inputs and outputs inverted is an OR gate (and vice versa)  --- Quote End ---    I think you have found the cause. I looked back at the schematic for my circuit and realised that I had totally overlooked my LED. I thought it was using an NPN transistor to drive it but it was in fact a PNP transistor. This means that my circuit has two naturally high inputs and one naturally high output. Thus making an OR gate operation, I rewrote part of the code to this out_1 <= ~in_1 & ~in_2; Now my circuit acts like an NAND gate (better but not quite). Do you know a way in which I can now further improve this to be a AND gate operation? Many thanks for your help!

[Altera_Forum]

Found a solution to my own problem! I invert the inputs and then the output which gives a normal gate operation. out_1 <= ~(~in_1 & ~in_2); Many thanks for your help!

[Altera_Forum]

Which means the inputs are active low (e.g. if it is a push button it means you get a zero when the button is pressed), and the output is inverted (e.g. the LED is driven by a n-channel FET, NPN transistor, or connected with anode to VCC and cathode to the pin). 

 The boolean reduction of your ~(~a & ~b) is simply (a | b), so if all inputs and the output have inverted meaning then you need to do the OR function.