Very basic SignalTap question

[Altera_Forum]

Hello, 

 I have inherited an old Cyclone II design which is mainly implemented in schematic. I am staying with the older version of Quartus for now (9.1) since there's a lot of native simulation files.  I'm trying to use SignalTap (using the MegaWizard) but can't seem to achieve a very simple thing :  - I have 17 bits of data to acquire - The whole design is clocked from a single 133MHz clock, and the data I'm interested in changes every 7.5us and there is an associated single clock cycle "NEW_DATA_PS" that I would, for example, connect to the wren pin of a RAM megawizard block if I was logging the data into memory.  I can't work out how to use this NEW_DATA_PS to qualify the acquisition of data into the SignalTap memory. The megawizard symbol has an acq_clk signal, but not an acq_clken. There is an acq_trigger_in , but this doesn't seem to work. What happens is that I seem to sample my data on every clock edge, and therefore see very little of use  If I try to drive acq_clk from the system clock AND'ed with NEW_DATA_PS the timing goes to hell (as I'd expected)  I can't help feeling I'm being really dumb here - but any help would be greatly appreciated.  Gary

[Altera_Forum]

As a first test just use the NEW_DATA_PS as the acq_clk. 

 If it's failing timing, try switch what edge of NEW_DATA_PS is used in the acquisition.  There's no requirement that the acq_clk be a real 50% duty cycle clock.  My biggest recommendation is to convert the schematic portions of the design to Verilog or VHDL as soon as you can. The schematics are nice for board designers, but their support is dropping quickly, and your simulation tools choices are very limited.  Pete

[Altera_Forum]

It's a bad idea to use the signal as an acquisition clock. If you get strange readings you'll never know if it is the design faults or sampling faults due to glitches. 

You can use a signal as a clock enable in Signaltap. Just sample your NEW_DATA_PS signal with the other 17, and then in the Signaltap configuration, look for the "storage qualifier" block. By default it is set to "Continuous", meaning that Signaltap will sample your signals on each clock cycle. If you set it to "Conditional" instead, then you will see a new column called "Storage Qualifier" just before the trigger column. There you can define an option that will tell Signaltap if it should sample the input or not. Set the NEW_DATA_PS storage qualifier to 1 and keep the other storage qualifiers to "don't care" and NEW_DATA_PS will act as a clock enable.

[Altera_Forum]

Thanks for the suggestions - very much appreciated.

[Altera_Forum]

Thanks Daixiwen, 

 I can find the storage qualifier option in the Megawizard. The choices are continuous or input port. Upon selecting input port the symbol has a pin "storage_enable". I connect this to NEW_DATA_PS and re-synthesize.  However, synthesis produces this error : Symbolic name "storage_enable" must be port of megafunction, macrofunction, primitive or state machine "sld_signaltap_component"  I must be doing something wrong

[Altera_Forum]

That's strange... don't you have anything else? Here are the choices I have in my Signaltap (Quartus 11.1 SP2)

[Altera_Forum]

Sorry for the delay - been putting out fires... 

No I don't. Let me try loading my project into Quartus 11 and see what happens. Thanks Gary

[Altera_Forum]

I loaded the project into V11.0 SP1 Web Edition and have only the same choices when I create a SigTap instance using the MegaWizard (see attached). 

I wonder what if any settings I'm missing

[Altera_Forum]

I just tried from the Megawizard and I got the same result than you. It looks like the Megawizard version of SignalTap lacks a lot of functionalities. If you use SignalTap from the Tools menu instead then you'll have a lot more options. Besides, contrary to the Megawizard version you don't have to instantiate and connect it yourself to your design. It will be automatically connected to all the signals you want to monitor.

[Altera_Forum]

Thank you - I'll try it that way.

[Altera_Forum]

If you instantiated SignalTap in your design directly using megawizard, you should be able to use the Input Port type still. In your simple case, you can connect NEW_DATA_PS to the storage_enable port. I tried it with a simple useless example as shown below and compiled successfully. 

 module one_wire ( input i, output o ); assign o = i; stp_test stp_test_inst ( .acq_clk ( i ), .acq_data_in ( {i} ), .acq_trigger_in ( {i} ), .storage_enable ( i ) ); endmodule  What is it different from yours fundamentally?