Trouble compiling my JK flip flop VHDL code!? "Syntax Error"

[Altera_Forum]

--The below code doesn't compile. I am given the following errors. Could someone help me troubleshoot this.  

 --ERRORS:  Error (10500): VHDL syntax error at lab4_jke.vhd(14) near text "if"; expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement Error (10500): VHDL syntax error at lab4_jke.vhd(14) near text "then"; expecting "<=" Error (10500): VHDL syntax error at lab4_jke.vhd(15) near text "then"; expecting "<=" Error (10500): VHDL syntax error at lab4_jke.vhd(17) near text "elsif"; expecting "end", or "(", or an identifier ("elsif" is a reserved keyword), or a concurrent statement Error (10500): VHDL syntax error at lab4_jke.vhd(17) near text "then"; expecting "<=" Error (10500): VHDL syntax error at lab4_jke.vhd(19) near text "elsif"; expecting "end", or "(", or an identifier ("elsif" is a reserved keyword), or a concurrent statement Error (10500): VHDL syntax error at lab4_jke.vhd(19) near text "then"; expecting "<=" Error (10500): VHDL syntax error at lab4_jke.vhd(21) near text "elsif"; expecting "end", or "(", or an identifier ("elsif" is a reserved keyword), or a concurrent statement Error (10500): VHDL syntax error at lab4_jke.vhd(21) near text "then"; expecting "<=" Error (10500): VHDL syntax error at lab4_jke.vhd(23) near text "if"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"       --CODE:   LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;   ENTITY lab4_jke IS  PORT(  S,R,J,K,CLK : IN STD_LOGIC;  Q : OUT STD_LOGIC;  NQ : OUT STD_LOGIC); END lab4_jke; ARCHITECTURE behavior OF lab4_jke IS BEGIN if (CLK'EVENT AND CLK='1') then if (J='0' AND K='0') then Q <= Q; elsif (J='1' AND K='0') then Q <= '1'; elsif (J='0' AND K='1') then Q <= '0'; elsif (J='1' AND K='1') then Q <= NOT(Q); END if; END if; END behavior;

[Altera_Forum]

LIBRARY IEEE; 

USE IEEE.STD_LOGIC_1164.ALL;   ENTITY lab4_jke IS  PORT(  S,R,J,K,CLK : IN STD_LOGIC;  Q : OUT STD_LOGIC;  NQ : OUT STD_LOGIC); END lab4_jke;  ARCHITECTURE behavior OF lab4_jke IS BEGIN  process(clk)  begin  if (CLK'EVENT AND CLK='1') then  if (J='0' AND K='0') then  Q <= Q;  elsif (J='1' AND K='0') then  Q <= '1';  elsif (J='0' AND K='1') then  Q <= '0';  elsif (J='1' AND K='1') then  Q <= NOT(Q);  END if;  END if;  end process; END behavior;

[Altera_Forum]

How can I incorporate the functionality of S "Set" and R "Reset" into my code?

[Altera_Forum]

A JK flip-flop doesn't have Set and Reset inputs. may be you want a preset and clear asynchronous inputs. In a FPGA you do that with a single asynchronous reset: 

 process(clr, clk) begin  if( clr = '1' ) then  q_reg <= '0';  elsif( clk'event and clk = '1' ) then  q_reg <= q_next;  end if; end process;   q_next <= '0' when ( j = '0' and k = '1' ) else ....etc