Vhdl jpeg decoder

[Altera_Forum]

Hi, I am working on a project where I need to implement a JPEG decoder to decode the JPEG output (1080p) of the camera (model: OV5642). My FPGA is DE1-SoC Cyclone V. I have been able to implement a jpeg decoder in the ARM processor using C, which works fine; but its speed does not satisfy my project's requirements. So, the solution that comes to my mind is to move the jpeg decoder to the FPGA side. However, I have not been able to find a jpeg decoder that merely works on the FPGA, not the processor. Actually, I have found one at opencores, however, the code uses ip cores from xilinx. My question is: do you know a jpeg decoder implemented in VHDL that I could use on an Altera FPGA? It would be very nice if you could state whether it is free or not. Thank you.

[Altera_Forum]

If its not on opencores, then it's not likely to be free. 

Jpeg decoding isn't something you usually need on fpga, as a single image isn't exactly a lot of data. Fpgas address much better at stream processing.  The Xilinx code you've found might be portable to altera. Otherwise you'll have to write your own core.

[Altera_Forum]

--- Quote Start ---  If its not on opencores, then it's not likely to be free. Jpeg decoding isn't something you usually need on fpga, as a single image isn't exactly a lot of data. Fpgas address much better at stream processing.  The Xilinx code you've found might be portable to altera. Otherwise you'll have to write your own core.  --- Quote End ---    I am sorry I did not make it clear that I am using the camera at video mode. So, in fact, I have a stream of jpeg images (30 fps) that I need to decode. My advisor suggested me to move the jpeg decoder to vhdl, which I have problems with. Thank you for your response.

[Altera_Forum]

Have you optimized c code?  

And where is the bottleneck? If you profiled your decoder you should know dataflow path.

[Altera_Forum]

--- Quote Start ---  Have you optimized c code?  And where is the bottleneck? If you profiled your decoder you should know dataflow path.  --- Quote End ---    Yes, I know my way around the c code and was able to optimize it. However, the thing is that the clock frequency of the hard processor system is just not enough after a certain point. For example, after optimizing the code, I have achieved 15 fps. So, since I need 30 fps, I turned my direction to finding a vhdl open source for jpeg decoding that can be run on an Altera board. Do you know anything like that? If there is not any, I will have to stick with the c code, of course. Thank you for your response.

[Altera_Forum]

Ok. You should sure that you saturated in c code optimization) no any suggestions  

If as you mentioned and you use appropriate data types and computing based on tabulated values You can verify according the standard optimization for loops, multiplication and even try some techniques for high performance computing cluster  I think if it applicable increasing speedup of algorythm  I read some reports about parallel processing for jpeg ls format But unfortunately I can't advise ready made for your problem

[Altera_Forum]

there are some on opencores, but you may have to adapt the interfaces (input/output) to the altera avalon domain or let qsys do that, if it is AXI3...