Warning (176441): The I/O pin <name> cannot meet the timing constraints due to conflicting require

[UMall1]

Warning (176441): The I/O pin <name> cannot meet the timing constraints due to conflicting requirements. The I/O pin is a PLL compensated I/O, but the setup/hold requirements are in conflict with the source PLL mode(source synchronous or ZDB).

I am using an ALTLVDS_RX module to read 5 LVDS pins using an LVDS clock.

I receive the above warning when I synthesize the design.

Why am I receiving the warning?

The ALTLVDS_RX module operates at 720Mbps, is 10-bits deep (for each pin) with a 90 degree phase difference between the data and clock signals. I can confirm that  a 90 degree phase difference does exits between the clock and the data lines (confirmed with a oscilloscope).

I am not receiving the bit pattern that I am expecting in my FPGA.

Can this be the reason?

Will it help to change to a BLVDS implementation?

The contents of my SDC file are below:

create_clock -period 2.778 [get_ports I_CLK_0]
create_clock -period 2.778 [get_ports I_CLK_1]
create_clock -period 10.00 [get_ports USB_CLOCK]
create_clock -period 100.00 [get_ports USB_I2C_CLK ]

# Automatically apply a generate clock on the output of phase-locked loops (PLLs)
# This command can be safely left in the SDC even if no PLLs exist in the design

derive_pll_clocks

set_input_delay -clock USB_I2C_CLK -max 20 [all_inputs]

set_input_delay -clock USB_CLOCK -max 5 [all_inputs]

set_output_delay -clock USB_I2C_CLK -max 20 [all_outputs]

set_output_delay -clock USB_CLOCK -max 5 [all_outputs]

[UMall1]

How or why am I implementing a PLL compensated I/O?

I have not specified any special parameter in my SDC or Pin definition files that would cause that inference. The ALTLVDS_RX mega-function does not allow one to choose the type of PLL used in the design.

When I was designing my ALTLVDS_RX mega-function I entered the phase difference between the data and clock signals to be 90 degrees. Is this causing the said inference?

[sstrell · Accepted solution]

You have -max on all 4 of your I/O contraints with no matching -min and you are using two different clock domains for all the same I/O pins, so the 2nd and 4th I/O constraints you have there are overriding the 1st and 3rd.  You'll see this in the timing analyzer Ignored Constraints report.

On top of that, the referenced clocks for the inputs should be virtual clocks (the clock that drives the external device that then drives the inputs to the FPGA), and the clocks for the outputs should be either virtual (the clock at the downstream device capturing the outputs, assuming a synchronous interface) or the generated clock outputs of the PLL (if this is a source synchronous output interface).

Take a look at these trainings to find your scenario:

https://learning.intel.com/developer/learn/course/internal/view/elearning/168/constraining-source-synchronous-interfaces

https://learning.intel.com/developer/learn/course/internal/view/elearning/841/intelr-quartusr-prime-pro-software-timing-analysis-part-4-io-interfaces