Warning: Found combinational loop of 1 nodes

Altera_Forum · ‎07-08-2010

how i can avoid this problem


library ieee;
USE ieee.std_logic_1164.all;
Entity dmux8 IS
PORT(
	S :	IN INTEGER RANGE 0 to 7;
	d :	IN STD_LOGIC;
	Y :	OUT STD_LOGIC_VECTOR(0 to 7)
);
END dmux8;
Architecture a OF dmux8 IS
BEGIN
dmux8:
PROCESS(d,s)
		BEGIN
		CASE S IS
		WHEN 0 =>
			Y(0) <= d;
		WHEN 1 =>
			Y(1) <= d;
		WHEN 2 =>
			Y(2) <= d;
		WHEN 3 =>
			Y(3) <= d;
		WHEN 4 =>
			Y(4) <= d;
		WHEN 5 =>
			Y(5) <= d;
		WHEN 6 =>
			Y(6) <= d;
		WHEN 7 =>
			Y(7) <= d;
		WHEN OTHERS => null;
		END CASE;
END PROCESS;
END a;

Altera_Forum · ‎07-08-2010

You have designed Y as a number of latches, that keep their previous content, when the respective output isn't selected. (Don't know if intententionally, but you did).

Latches are implemented by combinational logic loops. The Quartus design compiler suspects combinational loops as possible unwanted design implementation and thus releases a warning. If the latches have been created intentionally, just ignore the warning or disable the warning level.

You should consider, however, that the unselected outputs must be expected to change in an unpredictable way during the transitions of the select input and effectively latch accidental states, so you may want to change the design to get rid of the latching behaviour.

Altera_Forum · ‎07-08-2010

Basicaly you need:


WHEN OTHERS =>
           Y <= (others => '0');

And the combinatorial loop is at least simpler :).

To make it go away, clk the process.

Altera_Forum · ‎07-08-2010

--- Quote Start ---

amilcar

--- Quote End ---

i think i need to add this line for each state

Y <= (others => '0');

i added it as you said and still warnning message

but could you explain it i didn't see it before

--- Quote Start ---

FvM

--- Quote End ---

could you tell me what should i write here

Altera_Forum · ‎07-08-2010

--- Quote Start ---

WHEN OTHERS => Y <= (others => '0');

--- Quote End ---

doesn't change anything, because the case construct is already full decoded. No "others" cases are effectively left.

You can write a single Y <= (others => '0'); in front of case construct to break the combinational loop, if the implied logic behaviour is according to your intentions.

Altera_Forum · ‎07-08-2010

could you explain to me what is the combinational loop

Altera_Forum · ‎07-08-2010

You can view the implemented gate level logic of your original design in the Quartus netlist viewer. You see below, how a latch looks like, the feedback LE is called a combinational loop.

Altera_Forum · ‎07-08-2010

aha XP

thanks my frind

this the first time i see this tool can you tell me where can i fing the netlist tools please

Altera_Forum · ‎07-08-2010

On the bottom left window pane double click on "RTL viewer".

And yes, FvM is correct, you can only break it by writing Y <= (others => '0'); in *front* of (before) the case construct.

But the real question here is: What did you intend to achive with the code ?

Altera_Forum · ‎07-08-2010

i can't find it

what i did with this code is just for learning to implement dmultiplixer

Altera_Forum · ‎07-09-2010

See: Tools/Netlist Viewers/Technology Map Viewer

If you don't want to type too much text, you may find this form interesting:

dmux:
FOR I IN 0 TO 7 GENERATE
  Y(I) <= d WHEN I = S ELSE '0';
END GENERATE;

Altera_Forum · ‎07-25-2010

great thanks