Warning: No paths found for timing analysis

[Altera_Forum]

I'm writing a spi module,just a receiver. Few lines,but many warnings. 

The total logic elements is 0%. Can an get a answer about how to result the problem?  Code: module spi (input clk,  input cs,  input sdi,  output reg getdata,  output reg [7:0] recbuf    );  reg stsig = 0; reg [3:0] reccount = 7;  always @(cs) if(sdi) stsig = 0; else stsig = 1;  always @(posedge clk) begin if(stsig && reccount<8)  begin  recbuf[reccount] = sdi;  reccount = reccount - 1;  end else  begin  reccount = 7;  getdata = 1;  end end  endmodule   Warnings: Warning: Output pins are stuck at VCC or GND Warning: Design contains 3 input pin(s) that do not drive logic Warning: No exact pin location assignment(s) for 12 pins of 12 total pins Warning: Following 9 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. Warning: No paths found for timing analysis

[Altera_Forum]

getdata is obviously assigned 1 once and for all so it is stuck to VCC. 

 recbuf[] is assigned sdi when stsig is true yet when true sdi is zero so recbuf stays zero.

[Altera_Forum]

But sdi can be 1 or 0.So recbuf will be 1 or 0 according sdi,won't they?:confused:

[Altera_Forum]

when sdi is 1, stsig becomes zero 

when sdi is 0, stsig becomes one and if condition executes to assign to recbuf the zero sdi. if sdi becomes 1 then stsid is zero and else condition executes doing nothing to recbuf. so rebuf stays zero.

[Altera_Forum]

however, you might have point there because sdi and stsig change on the change of cs. So we need to look at that ...??

[Altera_Forum]

Yes.I just want to say it .

[Altera_Forum]

just simulated it in modelsim, seems working. 

Are you sure you are synthesizing the right files

[Altera_Forum]

Yes.No error occur when I compile it,but Total logic elements is 0%

[Altera_Forum]

I don't have quartus handy at the moment but I am a bit puzzled now. 

I know you are creating a latch at cs but I expect warning of latches rather than zero logic.  You may try avoid the latch by inserting your cs statemet on the clock edge just like other signals.  always @ (posedge clk)  if cs...  assuming it does not affect your functionality

[Altera_Forum]

Info: ******************************************************************* 

Info: Running Quartus II Analysis & Synthesis  Info: Version 9.0 Build 132 02/25/2009 SJ Full Version  Info: Processing started: Sat Jul 30 23:59:01 2011 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spi -c spi Info: Found 1 design units, including 1 entities, in source file spi.v  Info: Found entity 1: spi

[Altera_Forum]

Yes, it does not affect my functionality.But it will increase the time the logic elements judging them. 

In fact ,I am just a beginer leaning it for our Electronic Design Competition.If I can't solve the problem maybe I will get a spi communication module from our instructor.And I know FSM can work well from a book I read yesterday,but I don't want to use it while I'm leaning. Thank you very much for your suggestion,I will try it.

[Altera_Forum]

There might issue of tools here. While modelsim acepts your code it could be quartud thinks that stsig is assigned 0 and recbuf is assigned 7. you might better use init for that instead

[Altera_Forum]

But 

always @(cs) if(sdi) stsig = 0; else stsig = 1; is used to identify a start of a data receiving and datas will be delivered many times however initial just run once. It's too late now,I'll go sleeping. Thank you for your advise.Enjoy a good afternoon!