Warnings in blackjack code

[Altera_Forum]

I am seeing the below warnings in my program for black jack and dont know how to fix it 

 WARNING:Xst:1780 - Signal <d_card6> is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal <d_card5> is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal <d_card4> is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:737 - Found 4-bit latch for signal <d_card1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:737 - Found 4-bit latch for signal <d_card2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:737 - Found 4-bit latch for signal <d_card3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:737 - Found 4-bit latch for signal <p_card3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:737 - Found 4-bit latch for signal <p_card4>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:737 - Found 4-bit latch for signal <p_card5>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:737 - Found 4-bit latch for signal <p_card6>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:737 - Found 1-bit latch for signal <d_win>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:737 - Found 5-bit latch for signal <p_total>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:737 - Found 5-bit latch for signal <d_total>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:737 - Found 1-bit latch for signal <p_win>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:737 - Found 10-bit latch for signal <nextstate>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:737 - Found 1-bit latch for signal <d_win$mux0005>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:737 - Found 1-bit latch for signal <p_win$mux0005>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <d_win_mux0005>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch <d_win_mux0005> (without init value) has a constant value of 0 in block <bjstate>. This FF/Latch will be trimmed during the optimization process.   I have attached the code

[Altera_Forum]

This isn't a Xilinx help forum. 

   --- Quote Start ---  Signal <d_card6> is never used or assigned. This unconnected signal will be trimmed during the optimization process  --- Quote End ---   The warning means what it says. The signal is never read and assigned in an if branch that is never executed. The same or similar with the other warnings. There are obvious copy-and-past errors and apparently missing code parts.

[Altera_Forum]

c1 is never assigned any value, and you keep telling all those other signals to get the value of c1, which is nothing. 

with the other signals you are doing more than just assign c1 to it. So once you have assigned c1 a value, maybe the rest of the warnings will disappear aswell.

[Altera_Forum]

you have also not assigned all outputs in all cases of the state machine process - this will create latches. 3 ways to solve this: 

 1. Make sure all output signals are assigned in all states (annoying) 2. Give all output signals a default value before the state decode (best method if you insist on a 2 process state machine) 3. use a single clocked process state machine (safest and most reliable).

[Altera_Forum]

--- Quote Start ---  c1 is never assigned any value, and you keep telling all those other signals to get the value of c1, which is nothing. with the other signals you are doing more than just assign c1 to it. So once you have assigned c1 a value, maybe the rest of the warnings will disappear aswell.  --- Quote End ---     But I have mapped c1 to the value cardout from the random number generator value.

[Altera_Forum]

Then it obviously decided that the random number generator does nothing.

[Altera_Forum]

Have you checked that XST supports initialisation on signals as a valid way to program the power up value of registers?

[Altera_Forum]

Oooh.. Oops I din't see that portmap, I'm sorry for the confusion.That portmapping part didn't stand out. 

 Than its the part like FvM already mentioned, copy paste errors, you should check the values of the statements, they are not correct and therefore will never be assigned any value.