I am trying to create a macro file in modelsim. The file extension I need is .vh (Verilog include file). However, when I choose the file type as macro, I got a TCL file. Does anybody know how to create an include file with file extension of "vh"? Thanks.
This is my initial guess too. However, after I added the search path in the "Verilog and System Verilog", I was still told the include file can't be found.
