Weak Pull Up Setting

[ken-salt]

When compiling a Cyclone10 LP device, unused pins are set to “As input tri-stated with weak pull-up”.

Looking at the compiled report, the  display is different only for unused VREFB pins.

Is Weak Pull Up enabled for this pin?

[EngWei_O_Intel]

Hi there

You can refer to .pin file on the connection for the unused pins. The .pin file will be generated after completion of the Fitter compilation.

You can also refer to link below:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd10192006_240.html?erpm_id=1087861_ts1627911530394

Thanks.

Eng Wei

[ken-salt]

The pin number "AB4" enclosed in red is an unused VREFB pin. Is Weak Pull Up enabled?

[EngWei_O_Intel]

Hi

What view is this in Quartus tools?

As far as I understand, you could set the unused pin as shown here:

https://www.intel.com/content/www/us/en/programmable/quartushelp/13.0/mergedProjects/comp/comp/comp_tab_dp_unused_pins.htm

whereas the Weak Pull-Up Resistor shall be set through pin planner or assignment editor:

https://www.intel.com/content/www/us/en/programmable/quartushelp/13.0/mergedProjects/logicops/logicops/def_weak_pull_up.htm

Both are different setting. 

Thanks.

Eng Wei

[EngWei_O_Intel]

Hi there

I hope you are doing fine. We do not receive any response from you to the previous reply that have been provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Eng Wei