What files are needed for GTL simulation in Modelsim?

[Altera_Forum]

I always use Nativelink in Quartus II to do RTL and GTL simulation in Modelsim. Through that function, I only need to care write testbench and do some simple setting in Quartus, which is very easy. 

 But I want to learn how to do simulation directly in Modelsim without Quartus help. I tried RTL simulation and sucessfully. But in GTL simulation, I can't. I have questions as following two questions:  1. what files are necessary for GTL simulation? As I know, I don't need HDL design files (.v or .vhd), the files I need is .vo and .sdo files, which generated after full compilation and testbench file, right? If I want to simulate in slow 1.2V 85 mode, I only need to compile corresponding .vo and .sdo files, then do simulation, right?  2. This question confused me long time and I even confronted trouble during RTL simulation. How can I know what libraries I need to do GTL simulation for my design? I don't where I can check to know all the needed libraries.  Thanks!

[Altera_Forum]

Quartus produces one .vo/.vho and one .sdo which cover all the timing corners. 

For convenience, Quartus also produces a series of .vo/.vho for each specific corner. You only need compile that .vo/.vho and it will load .sdo information for that corner.  You also need to compile your testbenches' HDL files.  You'll need the FPGA's cell library. If the FPGA is Cyclone IV and you're using Verilog, then you need to load the cycloneiv_ver library.  You also need libraries for components that you use in your testbenches -- same as RTL simulation. Ie, if one of your testbenches uses a DCFIFO or some other MegaFunction, then you need to load the altera_mf_ver library as well.

[Altera_Forum]

--- Quote Start ---  Quartus produces one .vo/.vho and one .sdo which cover all the timing corners. For convenience, Quartus also produces a series of .vo/.vho for each specific corner. You only need compile that .vo/.vho and it will load .sdo information for that corner.  You also need to compile your testbenches' HDL files.  You'll need the FPGA's cell library. If the FPGA is Cyclone IV and you're using Verilog, then you need to load the cycloneiv_ver library.  You also need libraries for components that you use in your testbenches -- same as RTL simulation. Ie, if one of your testbenches uses a DCFIFO or some other MegaFunction, then you need to load the altera_mf_ver library as well.  --- Quote End ---    Thanks very much, if I use .vo file which cover all the timing corners, how can I decide which corner I want to simulate?

[Altera_Forum]

Hmm, my mistake. 

Quartus is producing multiple .sdo file, one for each corner. You'll need to use the proper .vo.  In case you do come across a 3 corner .SDF file, you use vsim -sdfmin/sdftyp/sdfmax to select the corner.

[Altera_Forum]

--- Quote Start ---  Hmm, my mistake. Quartus is producing multiple .sdo file, one for each corner. You'll need to use the proper .vo.  In case you do come across a 3 corner .SDF file, you use vsim -sdfmin/sdftyp/sdfmax to select the corner.  --- Quote End ---    Thanks very much!