Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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What is the procedure for using package file in Platform Designer?

JRoth3
Beginner
980 Views

Hi I am having an issue with package files in Platform Designer (Quartus 18.1). I am trying to create a new component in PD. My design consists of a number of vhdl files plus vhdl package files. I loaded all the files, including the package files, then ran "Analyze HDL Files". This produced the following error:

 

"Error: VHDL Use Clause error at Radent_Slave.vhd(37)": design lirary "dut_lib" does not contain primary unit "act_pkg" File: ../../../vhdl/Radnet_Slave.vhd Line: 37"

 

In order to debug the above error I copied the contents of the vhdl package to the top of each module file.But when I tried to load all the vhdl files without copying the package info into each module file I got the error above. So my question is:

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3 Replies
JRoth3
Beginner
147 Views

Correction: In order to debug the above error, I copied the contents of the vhdl package to the top of each module file. This worked fine after running "Analyze HDL Files".

 

But when I tried to load all the vhdl files without copying the package info into each module file I got the error quoted above. Screen shot of the error is also included.

 

Please advise how to use vhdl package files in Package Designer. Thank you!

KhaiChein_Y_Intel
147 Views
Hi JRoth3, Did you include the package in the HDL file? Example, use library_name.package_name.all Thanks.
KhaiChein_Y_Intel
147 Views

Hi JRoth3,

 

Is there any updates?

 

Thanks.

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