What is usage of "generate" in Verilog?

[Altera_Forum]

I am confused by the usage of "generate" in Verilog. I checked it online, find some demo codes like: 

  genvar index;  generate  for (index= 0;index < 64;index = index+1) begin : dq_delay  WireDelay#   (  .Delay_g (TPROP_PCB_DATA),  .Delay_rd (TPROP_PCB_DATA_RD),  .ERR_INSERT ("OFF")  )  u_delay_dq  (  .A (ddr3_dq_fpga[index]),  .B (ddr3_dq_sdram[index]),  .reset (~i_rst_p),  .phy_init_done (init_calib_complete)  );  end endgenerate  But what is the difference between using "generate" and only use "For" without "generate"? If I wrote the above codes as:  for (index= 0;index < 64;index = index+1) begin : dq_delay  WireDelay#   (  .Delay_g (TPROP_PCB_DATA),  .Delay_rd (TPROP_PCB_DATA_RD),  .ERR_INSERT ("OFF")  )  u_delay_dq  (  .A (ddr3_dq_fpga[index]),  .B (ddr3_dq_sdram[index]),  .reset (~i_rst_p),  .phy_init_done (init_calib_complete)  );  end  No "generate", what is the difference?  Thanks.

[Altera_Forum]

You still need the genvar index; statement in either situation. 

 Verilog 2005 made the generate/endgenerate keywords optional. Since the for loop appears outside of a procedural context, the extra keywords are unnecessary. The compiler is able to figure out that a for/if/case statement in a module context outside a procedural context is a generate block.  Verilog is a language full of implicit defaults. But sometimes it is better to document your intent by putting the extra keywords in there.

[Altera_Forum]

--- Quote Start ---  You still need the genvar index; statement in either situation.  Verilog 2005 made the generate/endgenerate keywords optional. Since the for loop appears outside of a procedural context, the extra keywords are unnecessary. The compiler is able to figure out that a for/if/case statement in a module context outside a procedural context is a generate block.  Verilog is a language full of implicit defaults. But sometimes it is better to document your intent by putting the extra keywords in there.  --- Quote End ---    Thanks, dave_59. So that means two codes I wrote are same in Verilog 2005, right?  Another question, you mentioned "for/if/case statement in a module context outside a procedural context is a generate block." Do you mean "if" or "case" out of "always"? I have never see that.  Thanks.

[Altera_Forum]

Yes, those construct have always been available together with for as a generate construct. See LRM 27.5 conditional generate constructs.

[Altera_Forum]

--- Quote Start ---  Yes, those construct have always been available together with for as a generate construct. See LRM 27.5 conditional generate constructs.  --- Quote End ---    Thanks, dave_59. I am still confused by this. Could you please give an example that "if/case" out of "always"? They must work with generate together, right? I mean if "if/case" is out of "always", "generate" can't be neglected like "for" statement. right?

[Altera_Forum]

There are examples in the LRM section I mentioned, particularity a for nested inside a case generate. Don't have a copy of the LRM? get one (go.mentor.com/get-1800)!

[Altera_Forum]

--- Quote Start ---  There are examples in the LRM section I mentioned, particularity a for nested inside a case generate. Don't have a copy of the LRM? get one (go.mentor.com/get-1800)!  --- Quote End ---    Thanks. I should get one. Do you know what is the latest version?

[Altera_Forum]

The one in the link I just posted.

[Altera_Forum]

--- Quote Start ---  The one in the link I just posted.  --- Quote End ---    Thanks. But where is the link? I did not see it.

[Altera_Forum]

Put your cursor over the words "get one"

[Altera_Forum]

Thanks very much.