What means IC Fanout field

[VCher6]

Hello!

I ran in such problem:

Can’t find in documentation what Fanout in Interconnect row means.

In Cell row Fanout means fanout of output nets. But Fanout in IC row mysterious for me.

I ran into it, when investigated project with Hard Memory Controller IP-core.

Screenshot in attachment.

[Kenny_Tan]

You can try to right click it and locate it in chip planner. This way, you can see clearly where does those fanout go to.

[VCher6]

This fanout isn't displayed in Chip Planner.

[Kenny_Tan]

If you click correctly, you should be able to click on the bottom left signal to see the fanout connection.

Try not to select any signal in the time quest when you locate it to chip planner.

[VCher6]

When I "Report Path in Chip Planner" and then double click on exact node in "Locate History" block, and click on "Generate Fanout Connections", I recieve Fan-out which located in "CELL" row below or above orange framed row, and NOT in "IC" row.

(Yes, I have counted for 200 arrows =)

[VCher6]

What do you mean under "bottom left" signal?

[Kenny_Tan]

If you point to the bottom left, you should be able to locate the lavstwrclk right? click on it you should be see where it goes to in the chip planner. I believe it is a location of the PLL for the HMC hybrid memory cube.

[VCher6]

Maybe we have some misunderstanding.

I don't want to see where goes the connection, I wanna understand what mean numbers in row (which framed orange on picture). This number is NOT the fanout of certain cell because of it presented in the next or previous rows.

For a huge variety of nets in project IC fanout is 1. Because of what fanout for this ICs is more than one?

Thank you!

[Kenny_Tan]

Can you attached your design.qar here? I will look into it. Without having the design, it will be hard to look into it.

[VCher6]

http://www.alterawiki.com/wiki/File:Cvrefdesign.zip

There is project from AlteraWiki.

After compilation open "Compilation Report" and report timing in TimeQuest from "TimeQuest Timing Analyzer" -> "Slow 1100mV 85C" -> "Setup Summary" -> "clk_clk".

First path contains node with IC Fanout = 10, like on screenshot from first post of this thread.

[Kenny_Tan]

Thanks,, I can see it.. IC means that InterConnect routing. Cell you can find it in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-timing-analyzer.pdf page 3.

[VCher6]

Sorry, but I can't see on this page clarification about interconnect fanout.

Can you clearly clarify what means that numbers (IC Fanout)?

[Kenny_Tan]

https://courses.engr.illinois.edu/ece411/sp2019/mp/qts_qii53018.pdf page 7-55 got specify on it. It just means by the interconnect(element) fanout.