If you click correctly, you should be able to click on the bottom left signal to see the fanout connection.
Try not to select any signal in the time quest when you locate it to chip planner.
When I "Report Path in Chip Planner" and then double click on exact node in "Locate History" block, and click on "Generate Fanout Connections", I recieve Fan-out which located in "CELL" row below or above orange framed row, and NOT in "IC" row.
(Yes, I have counted for 200 arrows =)
Maybe we have some misunderstanding.
I don't want to see where goes the connection, I wanna understand what mean numbers in row (which framed orange on picture). This number is NOT the fanout of certain cell because of it presented in the next or previous rows.
For a huge variety of nets in project IC fanout is 1. Because of what fanout for this ICs is more than one?
There is project from AlteraWiki.
After compilation open "Compilation Report" and report timing in TimeQuest from "TimeQuest Timing Analyzer" -> "Slow 1100mV 85C" -> "Setup Summary" -> "clk_clk".
First path contains node with IC Fanout = 10, like on screenshot from first post of this thread.