The short answer is no. (You can probably skip analysis and synthesis, and just rerun the fitter, timing analysis and assembler, but the fitter is probably the bulk of your time anyway.)
You could manually reroute this signal in the chip-editor, but I think that would take close to 18 minutes to do anyway once you figured out how to use the tool. If you were doing incremental compilation, you could probably shorten it, but a design that takes 18 minutes to compile probably won't benefit much from that flow, just because the compilation overhead is probably a good bulk of your compile time. (Although it may feel long, 18 minutes isn't bad at all. Wait until you have a 24 hour compile, and then you really need to plan for quicker compiles.)
(And you may ask why the fitter doesn't just recognize this change and change that one thing. For this particular scenario, it might actually be possible with a specialized algorithm, but trying to "recognize changes" and only refit those changes has been an area of work by all FPGA companies and I don't think anyone has a perfect flow. In reality, it's a much more complex problem then it appears to be on first glance. The incremental compilation flow works, but requires the user to set up their design into partitions which gives Quartus information as to what has changed and what hasn't.)
