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When I try to constrain the path between two FPGA pins with a skew of 2ns between max and min delay values.It time closes if i run Time quest analyser for some values.But when I run full compilation it fails with a different delay value

SK_VA
Beginner
800 Views

I am trying to constrain the max delay and min delay between an input pin and an outpin in FPGA so that under PVT conditions skew between max and min delay values be between 2-3 ns.

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4 Replies
mfro
New Contributor I
90 Views

I guess you should try and rephase your question.

 

At least I am unable to understand what you are asking.

AndyN
New Contributor I
90 Views

What are the specific constraints that you are using? Can you share them here?

SK_VA
Beginner
90 Views

set_max_delay -from [get_ports {input_pin}] -to [get_ports {output_pin}] 9.6

set_min_delay -from [get_ports {input_pin}] -to [get_ports {output_pin}] 3.2

 

this is the constraint I am using

 

sstrell
Honored Contributor III
90 Views

Is there just combinatorial logic between the pins or are you trying do this across registers?

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