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New Contributor I
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When using quartus_ipgenerate I get an error stating "Argument list too long" on Linux.

In the directory where my chiptop.qpf file is I'm trying to use this command specifically: "quartus_ipgenerate chiptop --generate_project_ip_files --synthesis=vhdl --clear_ip_generation_dirs".

 

However when I do this I get two error messages:

/opt/altera/18.0/quartus/bin/quartus_ipgenerate: line 63: /opt/altera/18.0/quartus/bin/quartus_ipgenerate: Argument list too long

 

/opt/altera/18.0/quartus/bin/quartus_ipgenerate: line 63: /opt/altera/18.0/quartus/bin/quartus_ipgenerate: Success

 

 

Any suggestions on how to proceed would be very helpful, thank you.

 

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Employee
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https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/archives/qts-qpp-5v1..., 9.19.12, pg 603. Try again using quartus_ipgenerate --generate_project_ip_files --synthesis=vhdl --clear_ip_generation_dirs chiptop
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New Contributor I
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Thank you for the suggestion GNg, unfortunately that gives the same results as the order in my initial question.

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Employee
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I didnt see any error when tested on a design. ***************************** Info: Command: quartus_ipgenerate --generate_project_ip_files --synthesis=vhdl --clear_ip_generation_dirs top Info: Using INI file /home/gbng/quartus.ini Info: Found 4 IP file(s) in the project. Info: IP file /data/gbng/test_ipgenerate/test_S10/mult_w8.ip was found in the project. Info: IP file /data/gbng/test_ipgenerate/test_S10/multi_adder_test.ip was found in the project. Info: IP file /data/gbng/test_ipgenerate/test_S10/ip/qsys_top/qsys_top_clock_in_0.ip was found in the project. Info: IP file /data/gbng/test_ipgenerate/test_S10/ip/qsys_top/qsys_top_reset_in_0.ip was found in the project. Info: Finished generating IP file(s) in the project. Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/data/gbng/test_ipgenerate/test_S10/mult_w8). Info: Skipped generation of synthesis files for the Platform Designer IP file /data/gbng/test_ipgenerate/test_S10/mult_w8.ip based on the current regeneration policy setting (Tools/Options/IP Settings). Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/data/gbng/test_ipgenerate/test_S10/multi_adder_test). Info: Skipped generation of synthesis files for the Platform Designer IP file /data/gbng/test_ipgenerate/test_S10/multi_adder_test.ip based on the current regeneration policy setting (Tools/Options/IP Settings). Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/data/gbng/test_ipgenerate/test_S10/ip/qsys_top/qsys_top_clock_in_0). Info: Skipped generation of synthesis files for the Platform Designer IP file /data/gbng/test_ipgenerate/test_S10/ip/qsys_top/qsys_top_clock_in_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings). Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/data/gbng/test_ipgenerate/test_S10/ip/qsys_top/qsys_top_reset_in_0). Info: Skipped generation of synthesis files for the Platform Designer IP file /data/gbng/test_ipgenerate/test_S10/ip/qsys_top/qsys_top_reset_in_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings). Info: Quartus Prime IP Generation Tool was successful. 0 errors, 3 warnings Info: Peak virtual memory: 947 megabytes Info: Processing ended: Tue Apr 9 19:29:16 2019 Info: Elapsed time: 00:00:12 *********************************** Could you attach the full generation message?
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New Contributor I
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When I run the command with the wording order as you suggested it takes approximately 3 minutes and the only info that is printed to the terminal are the two lines in my original question, nothing else.

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Employee
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Please check if Quartus environment variables in your PC that match the Pro version installation. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/support/kdb/downloads/rd01292013_416/s...
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