Where is "EMIF IP byte enable option"?

[Altera_Forum]

Hi! I have a SoC FPGA board (DE1 SoC) and did a setup using AVALON MM reading and writing 8bit from the HPS (Linux), now I wanted to extend the bit width to 128bit. When I generated the component setup in QSYS I ran into the following warning about byteenables: http://www.altera.com/support/kdb/solutions/rd07142014_810.html 

 Warning: System.hps.h2f_lw_axi_master/control.avalon_slave_0: control.avalon_slave_0 does not have byteenables. Writes from narrow master hps.h2f_lw_axi_master may result in data corruption.   As a fix, now I would like to turn on the "EMIF IP byte enable option" in the HPS "edit" menu. But I can't find it directly. Please, I'm still very new to FPGA and hardware development, can anybody tell me what to turn on exactly to have the "EMIF IP byte enable option" enabled and where to find it?

[Altera_Forum]

The knowledge base article you linked to is talking about a specific problem with using the Altera DDR3 controller under some conditions. 

 The actual error message you posted sounds more like a problem with the custom IP that you have added in your system. If this is true, then this is an issue you will need to resolve in your _hw.tcl and .v by adding support for byteenable's.

[Altera_Forum]

Thank you, my problem solved itself somehow going through the setup again - initially I used 8bit for the avalon pins, then tried to extend them to 32bit, that's where I saw this warning. Rechecking, now it does not throw this warning again. About the _hw.tcl - actually I never changed anything in such a file. Do you have a description how to work / debug this _hw.tcl?

[Altera_Forum]

--- Quote Start ---  Thank you, my problem solved itself somehow going through the setup again - initially I used 8bit for the avalon pins, then tried to extend them to 32bit, that's where I saw this warning. Rechecking, now it does not throw this warning again. About the _hw.tcl - actually I never changed anything in such a file. Do you have a description how to work / debug this _hw.tcl?  --- Quote End ---    What tutorial or manual are you following for creating your custom IP components? It should explain what the .tcl file is and it's importance.

[Altera_Forum]

Oh, I'm following various tutorials. I understand that building, pin assignment, and AFAIR all that is done in Quartus II ends up to be a TCL command which eaqually could be written directly, as well. It is true that most of the tutorials mention this point. I can't see, though, how to debug the TCL on the other side, if it was buggy.  

 If you have a tutorial/link that talks more about how to work with the _hw.tcl, I would appreciate to know! :)

[Altera_Forum]

Try starting with this one and/or it's prerequisites: 

http://www.altera.com/education/training/courses/oqsys3000

[Altera_Forum]

Wow! Thank you! BTW, I now had a look in some of my _hw.tcl files, to see if I can understand something. But it says quite at the beginning of each file: 

1# TCL File Generated by Component Editor 13.1 2# Sun Nov 02 00:02:19 CET 2014 3# DO NOT MODIFY ...   Is that "DO NOT MODIFY" not serious?