I have a design which `includes a header file which has `defines for default mode, say:`define ASIC_VERSION 32'h00000001I have an "override" in my .qsf to specify the FPGA build, say:set_global_assignment -name VERILOG_MACRO "ASIC_REVISION=32'h12345678" However, when I map I get this warning:Warning (10886): Verilog HDL macro warning at ...defines.v(line): overriding existing definition for macro "ASIC_VERSION", The `include file is overriding the .qsf! This is precisely the opposite of my intention. Is there any modifier to make sure that the .qsf file wins? Thanks, Tom
`ifndef ASIC_VERSION `define ASIC_VERSION 32'h00000001 `endifwill define ASIC_VERSION only if it is not currently defined (by the .qsf file) ( replaced `ifdef ... `else with `ifndef )
I did indeed try the ifndef guard around the Verilog `defines - fails same regardless of load order.Failure is the Warning (10886) cited above and the fact that I want the .qsf VERILOG_MACRO definitions to win - not the Verilog. Strangely, in the .flow.rpt it shows the definitions I want. I get the warnings and then in the actual implementation I see that Verilog won out.