Why I cannot see the my state machine in the statemachine viewer?

Altera_Forum · ‎01-10-2011

Hi all,

I'm new in FPGA and Quartus EDA tools. I tried to design a simple state machine with the verilog code. It can be simulated successfully, but I don't think it was actually recognized as a State Machine because it is not shown in the statemachine viewer.

Is there any protocols I should follow while I am coding so that I can view the state machine in the viewer?

Thanks in advance.

My codes:


module statemachine(Y,reset,clock,X);
    // Input Port(s)
    input Y;
    input reset;
    input clock;
    // Output Port(s)
    output X;
    reg state,nextstate;
    reg X;
    
    parameter state0=0;
    parameter state1=1;
    always@(Y,state)
    begin
    if(state==state0)
    X=0;
    else if(state==state1)
    X=1;
    if(state==state0)
      if(~Y)
        nextstate=state1;
    if(state==state1)
      if(Y)
        nextstate=state0;
        
        
    end
    
    always@(posedge clock ,negedge reset)
    begin
    if(~reset)
    state<=state0;
    else
    state<=nextstate;
    end
    // Additional Module Item(s)
endmodule

Altera_Forum · ‎01-10-2011

The state-machine only has two states and synthesis reduced it to a single register. You can see this single register in the RTL viewer (will have 'state' in its reference)

Try adding a third state, it will then show up as a state machine.