Why TimeQuest finds no setup paths for input constrained ports???

[Altera_Forum]

Hi 

I have an RGMII-MAC design, previously described here (http://www.alteraforum.com/forum/showthread.php?t=51437). I also explained my problem in this post (http://www.alteraforum.com/forum/showthread.php?t=51497#post212267), yet no answer! I hope this forum will help. Any idea is highly appreciated.  Now: I have constrained my input ports as below:   --- Quote Start ---  # input clock create_clock -name {phy_rx_clock} -period 8.000 -waveform { 0.000 4.000 } [get_ports {gphy_rxclk}] #virtual clock for phy create_clock -name phy_rx_clock_virtual -period 8.000 -waveform { 0.000 4.000 }  #generated clocks derive_pll_clocks  #clock uncertainty derive_clock_uncertainty  #input delay set rgmii_input_delay_min -0.50 set rgmii_input_delay_max 0.50  set rgmii_mac_inputs [get_ports { gphy_rxctl gphy_rxd [*] }]  set_input_delay -clock phy_rx_clock_virtual -min $rgmii_input_delay_min $rgmii_mac_inputs set_input_delay -clock phy_rx_clock_virtual -max $rgmii_input_delay_max $rgmii_mac_inputs set_input_delay -clock phy_rx_clock_virtual -clock_fall -min $rgmii_input_delay_min $rgmii_mac_inputs -add_delay set_input_delay -clock phy_rx_clock_virtual -clock_fall -max $rgmii_input_delay_max $rgmii_mac_inputs -add_delay  #clock groups set_clock_groups -asynchronous -group {clk_100_mhz} \ -group {u_pll|altpll_component|auto_generated|pll1|clk[0]} \ -group {u_pll|altpll_component|auto_generated|pll1|clk[1]} \ -group {u_pll|altpll_component|auto_generated|pll1|clk[2]} \ -group {u_pll|altpll_component|auto_generated|pll1|clk[3]} \ -group {u_pll_10_to_125|altpll_component|auto_generated|p ll1|clk[0]} \ -group {u_pll_phy_rx_clk|altpll_component|auto_generated|pll1|clk[0]} \ -group {u_s1ll|altpll_component|auto_generated|pll1|clk[0]} \ -group {u_s1pll|altpll_component|auto_generated|pll1|clk[1]} # false paths set_false_path -fall_from phy_rx_clock_virtual -fall_to u_pll_phy_rx_clk|altpll_component|auto_generated|p ll1|clk[0] -setup set_false_path -fall_from phy_rx_clock_virtual -rise_to u_pll_phy_rx_clk|altpll_component|auto_generated|p ll1|clk[0] -setup set_false_path -rise_from phy_rx_clock_virtual -rise_to u_pll_phy_rx_clk|altpll_component|auto_generated|p ll1|clk[0] -setup set_false_path -rise_from phy_rx_clock_virtual -fall_to u_pll_phy_rx_clk|altpll_component|auto_generated|p ll1|clk[0] -setup # multicycles set_multicycle_path 0 -setup -end -rise_fromphy_rx_clock_virtual -rise_tophy_rx_clock set_multicycle_path 0 -setup -end -fall_fromphy_rx_clock_virtual -fall_tophy_rx_clock  --- Quote End ---   When I want to see if timing is met using the following commands, the TimeQuest asserts that no setup paths are found! It does report relevant hold paths but not setup ones!   --- Quote Start ---  report_timing -setup -npaths 50 -detail full_path -from_clock {phy_rx_clock_virtual} report_timing -hold -npaths 50 -detail full_path -from_clock {phy_rx_clock_virtual}  --- Quote End ---   What could be the reason? Why no setup paths are found? How can I ensure that timing is met? Thanks