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Hi,
This might be a bug. Can you share your .qar file here?
To do this, go to Project->Archive Project.
Regards,
Nurina
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Hi,
Do you have any updates?
Regards,
Nurina
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Hello,
no sure what you are specifically asking.
Why do you expect different timing results for the codes?
Timing control statements in assignments are only effective in functional simulation or stimulus generation in testbenches.
They have no effect on hardware synthesis. Timing simulation is evaluating the behaviour of synthesized logic, timing control is ignored here.
Best regards
Frank
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If you are going to ask a question you need to provide a lot of supporting info if you want more than generic responses.
What version of Quartus?
What platform (ie, Windows, Linux, etc) and version?
What simulator (Questa I believe) and version?
Can you make a test bench that instantiates all the modules at once and runs them in parallel to display exact waveforms of each?
You say they are the 'same' but we really can't validate that assertion in the data you present.
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Hi,
As mentioned in above comments, delay cannot be synthesized, that's why you see the same waveforms.
However, you can use this in testbenches.
Regards,
Nurina
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Hi,
We do not receive any response from you on the previous reply provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 4/5 survey/
Regards,
Nurina

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