Why is my block "synthesized away"?

[Mirei]

I'm an FPGA newbie scratching the surface of all this stuff.

Could someone please have a look at the attached project?

I had it successfully running with "spi_slave.vhd" as top level entity and the according pin assignments.

Now I tried to set up a "BFD" following some old Altera tutorial (tt_my_first_fpga_3.pdf) and wanted to replace the direct clock input by a PLL.

Although all looks to me the same as e.g. in this example http://maximator-fpga.org/wp-content/uploads/2016/02/MAXimator-PONG-HDMI.zip the compiler keeps telling me that my PLL block has been "synthesized away", there is no clock input, and the input pins "do not drive logic".

What am I doing wrong?

[Abe]

There were few inputs/outputs that were unconnected. I've corrected them and also added few others.. Take a look at the Qar file and modify accordingly. Now, the PLL and other registers are not optimized away.

[Rahul_S_Intel1]

Hi ,

There were some unconnected ports that is the reason for not compiling.

Regards,

Rs