Why is my inout signal converted to output by eda netlist writer?

[Altera_Forum]

My simple test dut consists of the following code. When I run a compile on this code (Processing ->start Compilation) the netlist written by the EDA Netlist Writer has signal defined as output instead of inout. I am unable to figure out what I am doing wrong. Any hints or help in identifying the issue is welcome. 

 module test( input dir, inout signal, input clk, input rst_n ); reg intreg; always @(posedge clk or negedge rst_n)begin if (~rst_n) intreg<=1'b0; else begin if (dir) intreg<=signal; end end assign signal=dir?1'bz:intreg; endmodule   The generated netlist is   // Device: Altera 10M08SCE144C8G Package EQFP144 // // // This Verilog file should be used for ModelSim-Altera (Verilog) only // `timescale 1 ps/ 1 ps module test ( dir, signal, clk, rst_n); input dir; output signal; input clk; input rst_n;    the .v and .vo files are attached for reference.

[Altera_Forum]

Have you checked your design with the RTL Viewers and Netlist viewers? This will give you an idea how the logic/pin was implemented in the FPGA.

[Altera_Forum]

--- Quote Start ---  Have you checked your design with the RTL Viewers and Netlist viewers? This will give you an idea how the logic/pin was implemented in the FPGA.  --- Quote End ---    I tried compiling Altera's bidirectional port example I find that the results are not consistent, The first compile results in a netlist with an inout port, the second compile results in a netlist with an output port.  All I had to do is click Processing->StartCompilation twice to get these two results  https://www.altera.com/support/support-resources/design-examples/design-software/verilog/ver_bidirec.html

[Altera_Forum]

--- Quote Start ---  I tried compiling Altera's bidirectional port example I find that the results are not consistent, The first compile results in a netlist with an inout port, the second compile results in a netlist with an output port.  All I had to do is click Processing->StartCompilation twice to get these two results  https://www.altera.com/support/support-resources/design-examples/design-software/verilog/ver_bidirec.html  --- Quote End ---    I have attached the two netlists generated using the above process.  Observe the content of the /simulation/modelsim/bidirec.vo   grep -a2 "^output" */simulation/modelsim/bidirec.vo inout/simulation/modelsim/bidirec.vo-input clk; inout/simulation/modelsim/bidirec.vo-input [7:0] inp; inout/simulation/modelsim/bidirec.vo:output [7:0] outp; inout/simulation/modelsim/bidirec.vo-inout [7:0] bidir; inout/simulation/modelsim/bidirec.vo- -- output/simulation/modelsim/bidirec.vo-input clk; output/simulation/modelsim/bidirec.vo-input [7:0] inp; output/simulation/modelsim/bidirec.vo:output [7:0] outp; output/simulation/modelsim/bidirec.vo:output [7:0] bidir;

[Altera_Forum]

I just tried re-compiling both your code as well as the Altera example, and both times, I get the same logic inferred - Bidir IO . If you're getting inconsistent results, check the tool settings if you have modified any and revert back to Defaults.  

 I'm also using the latest QPrime 17.1. This should not happen irrespective of the tool version and number of times the same design is being compiled. The only way this can happen is if there's been some setting changed in the tool or some other constraints modified.

[Altera_Forum]

The zip file was created using tool version 17.0, I will recheck with 17.1 

In case it matters, my system is  %uname -a  Linux Dyumnin 4.13.0-16-generic# 19-Ubuntu SMP Wed Oct 11 18:35:14 UTC 2017 x86_64 x86_64 x86_64 GNU/Linux  For the Altera example code, I did not change any settings.  My Process was as follows. mkdir output cp bidirec.v output cd output {Launch Quartus} {Do File->New->New Quartus Prime Project} {select the device, project folder and verilog file} {Do Processing->StartCompilation} {Check netlist writer has generated inout port: YES} {Do Processing->StartCompilation} {Check netlist writer has generated inout port: NO}

[Altera_Forum]

I did compile both the projects in the zip file that you sent. Both have same results for me. I get BiDir ports in both and on multiple runs . No change in implementation.

[Altera_Forum]

The recommendation is to not have the conditional on the incoming signal. Just get rid of "if (dir)" in the always block.

[Altera_Forum]

Received a message from Intel confirming that they were able to reproduce the bug and have assigned it to the dev team. 

 Waiting for the workaround/fix.

[Altera_Forum]

I guess it was an issue with the Linux versions of the tool. Didn't see this in the windows versions.