Why is the LEC (Logic Equivalent Check) needed in the FPGA Flow?
There is no a P&R stage (as in ASIC flow)...
Is it not enough just to check the logs and reports of the synthesis tools in order to see the RTL was synthesized without problems?
Why is LEC stage involved in the FPGA flow? When is it required?
FPGAs do have P&R flows. All the cells are in fixed locations, but it needs to map the synthesised netlist to these cells and work out the routing between them.
So the synthesised netlist will have no routing information. A routed design doesnt necessarily meet timing.
Full FPGAs often struggle in timing where in an ASIC it may have more freedom in the layout and routing.
In reality though, while FPGA tools do allow simulation netlists at all stages of the design for whatever the customer wants to do, most FPGA engineers do functional simulation and have good timing specs. If the design meets timing, then assuming good design practice (fully synchronous - all IO constrained correctly) the design should work the same as the functional simulation.
So, as for the LEC tools, could you please provide an example when LEC can help (catch some bugs) while other tools are useless?
As for the FPGA flow, are LEC tools just involved in the RTL vs Netlist compare? What about verification of the mapped design (Netlist vs ma)?
Is there a post-mapped Netlist in FPGA (including timing information of the mapped design)?
How do I extract Pre-Mapped and Post-Mapped Netlists from Quartus?
I have never done any LEC in FPGA, and I dont know anyone who has.
Like I said, it has all been RTL simulation + good timing specs then program the chip and see if it works.