Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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midi (uart) input & midi parse (fpga newbee)


i am a newbe in fpga...


my project starts with a midi - input, its the first thing i have to make - in order to do and test things in the fpga, in order to learn


(by the way i bevore realized this project in max msp, then on uC C, but the midi-uart and routing - this basics, where done by scripts or functions, which where already there, so i know what i want, and now trying to achive it in a new and other way)


i know a midi input is basicly a optocoppler (isolation and levelshift to 3.3V)


the optocopplers output is then connectet to the fpga gpio pin (set as input)


in the fpga i now have to setup a uart, on the intel website are a few ips, but none for the cyclone10lp

in quartus i found 2: irD UART and RS232 UART - which one is the correct for this task?


when choosen the rs232, i got some settings to do in the ip:

avalon type: memory mapped, streaming ( i guess memory mapped?)

baudrate: 31250

prarity: none

start bit:1

data bit:8



if setuped correctly what is the output of the uart? (8bits? i gues it when i use memory mapped, i could somehow write into a memory, i guess the UART-ip takes some logic cells and save the 8 bits in it? which i then access outside the UARt-ip?)



--- the next thing i then need is to make a parser based on the 8 bits


best thing would be a example program that already uses a midinput, and do some stuff with it in it (for example a synthesizer, midimerger, midirouter, or anything else which uses midi inputs)



by the way the uart specs for midi are:

0mA=logical 1 (midi works with current swing, instead of rs232 voltage swing)

5mA=logical 0

31250 Baud +-1% 25Mhz 25 000 000/31250 = 800 Clocks per Cycle (to sample middle of bit)

2uS max Rise/Fall Time No Handshake No Parity


thx for any help

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