Hi,recently, I designed a double-precision floating-point FFT project using Quartus Prime 21.1. This project includes 1-PORT-ROM IP, Bit-Intel FPGA IP and FFT Intel IP.
ROM IP outputs 256 point 64-bit double precision floating-point numbers, which are sinusoidal signals with amplitude of 100 and frequency of 200. Signal data_real_in,validin, validout1,validout2 as shown in the figure below.
Data flows into Bit-reverse Intel FPGA IP before it flows into FFT Intel IP. In theory, the output of the FFT should be such that at frequency 200 the amplicon is 100.
HOWEVER, the output of FFT in Modelsim is much larger than 200 at a frequency of 200 and it is not 0 at other frequency components.
I wonder where I went wrong in design. If you know, can you please tell me? Thank you!!!