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17268 Discussions

Why the type converter does not work ?

Altera_Forum
Honored Contributor II
1,426 Views

In my design I need to do is convert a std_logic_vector signal to the integer signal for array index. Then I do following: 

 

 

use IEEE.NUMERIC_STD.ALL;  

 

generic 

C_SLV_ADWIDTH : integer := 6; -- This width is actual address width 

)  

 

constant C_NUM_REG : integer := 2 ** C_SLV_ADWIDTH; 

 

 

signal slv_addr : std_logic_vector(C_SLV_ADWIDTH-1 downto 0); 

signal slv_addr_integer : integer range 0 to C_NUM_REG;  

 

 

slv_addr_integer <= to_Integer(slv_addr); -- this convert data type std_logic_vector to integer 

 

But I get errors, why converter does not work?  

 

Thanks in advance. 

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4 Replies
Altera_Forum
Honored Contributor II
679 Views

 

--- Quote Start ---  

In my design I need to do is convert a std_logic_vector signal to the integer signal for array index. Then I do following: 

 

 

use IEEE.NUMERIC_STD.ALL;  

 

generic 

C_SLV_ADWIDTH : integer := 6; -- This width is actual address width 

)  

 

constant C_NUM_REG : integer := 2 ** C_SLV_ADWIDTH; 

 

 

signal slv_addr : std_logic_vector(C_SLV_ADWIDTH-1 downto 0); 

signal slv_addr_integer : integer range 0 to C_NUM_REG;  

 

 

slv_addr_integer <= to_Integer(slv_addr); -- this convert data type std_logic_vector to integer 

 

But I get errors, why converter does not work?  

 

Thanks in advance. 

 

--- Quote End ---  

 

 

to_integer(unsigned(x)); or 

to_integer(signed(x)); 

 

The choice is yours. I think you want the first
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Altera_Forum
Honored Contributor II
679 Views

Thanks very much, kaz. Yes, I want the first. I try what you suggested and it works.

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Altera_Forum
Honored Contributor II
679 Views

 

--- Quote Start ---  

Thanks very much, kaz. Yes, I want the first. I try what you suggested and it works. 

--- Quote End ---  

 

 

Great. Now it is your turn to explain to te forum why you need to cast unsigned (or signed) for std_logic.
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Altera_Forum
Honored Contributor II
679 Views

I define an new type which is an array: 

 

type array_reg is array (C_NUM_REG-1 downto 0) of std_logic_vector (C_SLV_DWIDTH-1 downto 0); 

 

Then I declare a signal: 

 

signal slv_reg : array_reg; 

 

slv_reg will be used as a group of registers whose number will be small, like 32, 64. Then I want to use input signal "slv_addr" as the address to reach the register. So I try to convert it to "slv_addr_integer " then use it as: 

 

a<=slv_reg(slv_addr_integer);
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