Will Quartus ever support Verilog hierarchical parameter referencing?

[Altera_Forum]

Hello, 

module p {  parameter x = some expresssion;  ... }  p p_inst();  localparam x = p.x;  This would be really useful i.e. read as essential for what I am trying to do. Anyone on the forum from Altera care to comment? This is supported in Modelsim. Is there a reasonable work-around (at the moment I have an elaborate system of include files to do this but it is a sticking plaster really).  Thank you.

[Altera_Forum]

Quartus does support it - but the syntax is different 

p# ({new_value}) p_inst();  Where {new_value} is the overriding value for that instance.  Also see http://www.asic-world.com/verilog/para_modules1.html  Cheers, Alex

[Altera_Forum]

--- Quote Start ---  Quartus does support it - but the syntax is different p# ({new_value}) p_inst();  Where {new_value} is the overriding value for that instance.  Also see http://www.asic-world.com/verilog/para_modules1.html  Cheers, Alex  --- Quote End ---   Hi, sorry for misunderstanding but I do not want to set a parameter, I want to refer to it i.e. read it.

[Altera_Forum]

Sorry, you did make that clear in your original post... 

 Pass the parameter value out of module p as a wire. Quartus will optimise it away given it's a constant. I'm sure that's tidier than 'an elaborate system of include files'.  I'm struggling a little as to why it's 'essential' to be able to retrieve the parameter value. Can you elaborate any more?  Cheers, Alex

[Altera_Forum]

Imagine an addition module which decomposes the addition in different ways depending on width. Small widths are done in a single cycle but larger widths are recursively decomposed into smaller chunks which takes extra clock cycles. The calling module needs to know when the result will be ready. Hence the need to read an "attribute" of the addition module, in this case "pipeline delay". Ideally this would be read only, perhaps by using a localparam (this works fine in Modelsim assuming it is actually compliant with the Verilog LRM). Yes, this could be done dynamically with a flag but my system pipeline is all statically arranged/aligned at elaboration time, not run time.

[Altera_Forum]

Delving into the LRM a bit further, I'm not sure it is actually legal code to assign anything other than a constant to a parameter or localparam definition. Having said that, the hierarchical reference does resolve to a constant in the end. 

 I do also get this warning in Quartus: "Warning(16820): Verilog HDL warning at signedmultiply.v(526): constant expression cannot contain a hierarchical identifier "  I'm not sure if this means it is illegal or "we don't support that", since Modelsim obviously does so.

[Altera_Forum]

I can only suggest you add a parameter at your top level, specifying the pipeline delay, for each module you instantiate. Prior to elaboration, these pipeline delays are know and fixed - you know what modules you're instantiating and associated delays. I appreciate this is only a little better than hard coding these static values into your higher level code. However, it would make for more readable code. 

 Cheers, Alex

[Altera_Forum]

I have a similar problem. I organize the parameters into a struct, and then pass the struct. as a parameter into an interface. 

  typedef struct packed  {  int unsigned DATA_WIDTH;  int unsigned ADDR_WIDTH;  } cfg_s;  interface some_if  # (parameter cfg_s CFG = some_if_pkg::CFG_DEFAULT)  when trying to access CFG.DATA_WIDTH, I get a "constant expression cannot contain a hierarchical identifier." from quartus  Questa has no problems with this.

[Altera_Forum]

I raised an SR for this. Altera's reply was that according to the LRM, they are correct i.e. you cannot reference a constant expression using a hierarchical reference. SR closed. Strange that Modelsim does allow this though. Obviously a difference of opinion on that one.