Xcelium support for Agilex P-tile PCIe simulations

[binupr]

Hi there,

I am creating a PCIe controller targeting Agilex F series device. Wanted to run the example design on Cadence Xcelium simulator. When I ran the generated script for Xcelium, I got the below error:

• xmsim: *F,NOSNAP: Snapshot 'pcie_ed_tb.pcie_ed_tb' does not exist in the libraries.

When I searched the Intel knowledge base, I came across the link R-tile Xcelium fix.

Guess this has been fixed for P-tile devices as well. But I also found the below message in the link.

• Note: The Xcelium simulator support is only available in devices with the suffix R2 or R3 in their ordering part numbers (OPNs).

Does this mean Xcelium is not fully supported for P-Tile or R-Tile Simulations? Will there be a fix in future? Btw. I am running Quartus 23.1 Pro.

Thanks

Binu

[wchiah]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

Regards,

Wincent_Intel

[wchiah]

Hi

The solution is provided, and the R-tile design is able to run in Xcelium simulation environment.

We have not hear from you and this Case is idling. It is not recommended to idle for too long.

Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause

Hence, This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

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Regards,

Wincent_Intel

[binupr · Accepted solution]

Hi Wincent,

Apologies for the delay in responding to your prior follow-up email.

Yes, you can close this ticket.

Thank you for the support.

Regards

Binu