Zero total logic elements for top module instantiate lower module

[Altera_Forum]

Hi all, 

I'm getting zero total logic elements in my top module compilation, if I set my lower level module set top level entity and compile it, there total logic elements showing some number.  Any idea why?  Thanks!

[Altera_Forum]

No design outputs depend on the implemented logic, clocks unconnected or something like this.

[Altera_Forum]

I'm coding a processor, and my processor don't have output, I just do RTL simulation and monitor on the value inside register file and memory. This will have zero total logic elements as well?

[Altera_Forum]

RTL simulation doesn't deal with logic elements. What's the problem?

[Altera_Forum]

A design that has no outputs basically does nothing. Hence why the synthesisor removes all logic. How do you expect to monitor it on the real FPGA if it has no outputs?