about SDC file

[Altera_Forum]

Usually ,, we use the .sdc file in analysing the timing by Timequest. however, I always don't know that if the codes in the .sdc file can change the fitter(placing and routing) while we using the .sdc file in quartusii? thanks a lot......:):)

[Altera_Forum]

The fitter's major priorities are to get a legal fit that satisfy the .sdc requirements. Look at the following for more details on the fitter: 

http://www.alterawiki.com/wiki/the_quartus_ii_fitter_and_seed_sweeps (But to keep it simple, the answer is yes...)

[Altera_Forum]

and all you need to do is include the .sdc file as one of your source files in the design.

[Altera_Forum]

and can you give me a simple example about a sentence in the .sdc file is used to change the fitting? thanks a lot !...

[Altera_Forum]

There are not specific SDC commands to change the fitter. 

 the .sdc file is used to describe the constraints that the design needs to meet.  The tools will try to find a solution that meets those constraints. Ie, a solution that doesn't yield violations in TimeQuest.  So, anything you write in the SDC may impact the fitter.

[Altera_Forum]

Think of it like this, very simplified. It helped me a lot to grasp what was going on. 

  Using VHDL or whatever you describe some behavior, like a register.  In your RTL simulation rising edge of clock and data would arrive at the register at the exact same time, and the register will hold the data. Real life does not work like that.   What the tool does when synthesizing is to skew or delay the clock a bit, so that data arrives at the register first - then a bit later the rising edge of the clock arrive and the register will work as intended.  The SDC file can be used to describe the clocks in your design - and also set up constraints of your input/output ports etc etc. This helps the synthesizer resolve how it should all be wired together.   M.

[Altera_Forum]

One note, Morenk, is that the fitter does very little clock skew manipulation. (There is an option called Enable Beneficial Clock Skew that does this, but only enables a single dedicated skew as the clock enters the LAB, which sometimes can't be done due to other registers in the LAB that can't handle it). A better way to think of it is that the clock trees are laid out first, with an effort to get the least amount of skew. That's the main goal for the global clock trees. With minimal skew, the clock period dictates how long the data path can be, and the fitter does a TON of work to try and shorten the data path. So the emphasis is on the data path, not the clock skew.

[Altera_Forum]

but can anyone give me a simple exaple about this ? thanks.....