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Altera_Forum
Honored Contributor I
798 Views

adc_mic_lcd demonstration on NEEK max10

im looking at the code, from terasic max10 neek demonstration files. 

and trying to understand what purpose it serves: 

module MAX10_ADC ( input SYS_CLK , input SYNC_TR, input RESET_n , input ADC_CH , output reg DATA , output DATA_VALID, input FITER_EN ); wire sys_clk; wire response_valid; wire command_startofpacket; wire command_endofpacket; wire command_ready; wire response_channel; wire response_data; wire response_startofpacket; wire response_endofpacket; reg cur_adc_ch; reg adc_sample_data; assign DATA_VALID =response_valid; // continused send command assign command_startofpacket = 1'b1; // ignore in altera_adc_control core assign command_endofpacket = 1'b1; // ignore in altera_adc_control core // --adc_sample_data: hold 12-bit adc sample value // --max10 adc chanel adc_qsys u0 ( .clk_clk (SYS_CLK ) ,// ADC_CLK_10), .reset_reset_n (RESET_n), .modular_adc_0_command_valid (SYNC_TR), .modular_adc_0_command_channel (ADC_CH), // .channel .modular_adc_0_command_startofpacket (command_startofpacket), // .startofpacket .modular_adc_0_command_endofpacket (command_endofpacket), // .endofpacket .modular_adc_0_command_ready (command_ready), // .ready .modular_adc_0_response_valid (response_valid ), // modular_adc_0_response.valid .modular_adc_0_response_channel (response_channel ), // .channel .modular_adc_0_response_data (response_data ), // .data .modular_adc_0_response_startofpacket (response_startofpacket), // .startofpacket .modular_adc_0_response_endofpacket (response_endofpacket), // .endofpacket .clock_bridge_sys_out_clk_clk (sys_clk) ); //--data latch reg response_valid_r ; reg ADC_RD0,ADC_RD1,ADC_RD2,ADC_RD3,ADC_RD4,ADC_RD5 ; reg CNT ; always @ ( posedge sys_clk ) begin response_valid_r <= response_valid ; if (~response_valid_r & response_valid) begin { ADC_RD0,ADC_RD1,ADC_RD2,ADC_RD3,ADC_RD4,ADC_RD5 } <= { ADC_RD1,ADC_RD2,ADC_RD3,ADC_RD4, ADC_RD5,response_data }; DATA <= FITER_EN ? (ADC_RD0+ADC_RD1+ADC_RD2+ADC_RD3+ADC_RD4+ADC_RD5)/6 : response_data ;//response_data; end end endmodule  

im trying to figure out what the last paragraph is doing 

from my understanding 

always @ ( posedge sys_clk ) begin response_valid_r <= response_valid ; if (~response_valid_r & response_valid) begin { ADC_RD0,ADC_RD1,ADC_RD2,ADC_RD3,ADC_RD4,ADC_RD5 } <= { ADC_RD1,ADC_RD2,ADC_RD3,ADC_RD4, ADC_RD5,response_data }; DATA <= FITER_EN ? (ADC_RD0+ADC_RD1+ADC_RD2+ADC_RD3+ADC_RD4+ADC_RD5)/6 : response_data ;//response_data; end end  

the if statement is never successbecause the if is always '0'. 

 

thanks.
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Altera_Forum
Honored Contributor I
35 Views

I've found there's quite a large amount of Terasic's 'reference' code that could do with some attention - although this isn't that bad... 

 

Don't be fooled by the fact that the line of code updating 'response_valid_r' might appear to be immediately before it is tested. You could put the statement updating 'response_valid_r' after the if statement and realise the same behaviour. Both statements are evaluated on each rising edge of the clock. The test where the conditional statement is true will be when 'response_valid_r' is low and 'response_valid' has gone high, the clock cycle before 'response_valid_r' has been updated (high). 

 

Ultimately, it's looking for a rising edge on 'response_valid'. Thus you end up with a single clock cycle where the 'if' statement is true. 

 

If in doubt, simulate that little block of code. 

 

Cheers, 

Alex
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