- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Generate example design with
active channels : 10/29GE channels
single channel
RSFEC enabled : first_lane3,
ANLR enabled
example design : design completes build , fails to load
Oct 15, 2020 9:12:48 PM com.altera.systemconsole.unifiedtoolkit.InstanceLogger receiveMessage
SEVERE: An error occurred while running script "init_toolkit
": av_top_jtag_master: master_read_32: This transaction did not complete in 60 seconds. System Console is giving up.
while executing
"master_read_32 $master_claim_path $byte_address 1"
(procedure "reg_read" line 28)
invoked from within
"reg_read $base_addr $base_kr_ctrl"
(procedure "common_driver_pkg::read_fec" line 14)
invoked from within
"common_driver_pkg::read_fec"
(procedure "refresh_gui" line 44)
invoked from within
"refresh_gui"
(procedure "init_toolkit" line 18)
invoked from within
"init_toolkit"
Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
Can you share more detail so that I can debug and duplicate your issue in house
- May I know which Quartus version that you used ?
- Which FPGA product that you used ? Can you share with me the Ethernet IP QSYS file or IP file ?
- Which Intel dev kit board that you used ? Did you configured the dev kit board on board switch setting correctly ?
- Can you elaborate further on the procedure steps on how you run the software tool ? Which software tool to be precise here ?
Thanks.
Regards,
dlim
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
HI,
I am closing this case since I have not hear back from you for close to one month.
Regards,
dlim
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page