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altera_sc_fifo problem - invalid first transfer

Altera_Forum
Honored Contributor II
‎02-11-2016 07:47 PM
1,200 Views

Hello everyone! 

 

I am developing design, which includes Altera's Single Clock FIFO implementation. Unfortunately it doesn't seem to work properly. 

 

In my earlier projects valid transfers took place only when out_ready signal was active. Here (screen), first part of the packet data ('aaaa....') is transfered before out_ready is set to '1' (and in consequence is lost). 

 

Has anybody met such situation? I will appriciate every suggestions, how to solve my problem... 

 

I attach screenshot from simulation in Modelsim ASE 10.1d and my testbench. 

 

matey22
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Altera_Forum
Honored Contributor II
‎02-11-2016 07:53 PM
370 Views

Hi again,  

 

by mistake I created same thread twice, please delete this one. 

 

matey22
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