altera_sc_fifo problem - invalid first transfer

Altera_Forum · ‎02-11-2016

Hello everyone!

I am developing design, which includes Altera's Single Clock FIFO implementation.

Unfortunately it doesn't seem to work properly. In my earlier projects valid transfers took place only when out_ready signal was active.

Here (screen), first part of the packet data ('aaaa....') is transfered before out_ready signal is set to '1' (and in consequence is lost).

http://www.alteraforum.com/forum/attachment.php?attachmentid=11807&stc=1

Has anybody met such situation ? I will appriciate every suggestions.

I attach screen with simulation in Modelsim ASE 10.1d and my testbench.

matey22

Altera_Forum · ‎02-11-2016

The picture is very low resolution - can you post a bigger one?

Altera_Forum · ‎02-11-2016

Here it is, I hope it will be ok now.

Altera_Forum · ‎02-11-2016

Actually - looking at your (small) picture and testbench code - I bet it's a delta race problem. Initial block uses# time intervals and is not synchronous to the clock - so the out_ready signal is actually 1 when the clock changes and hence you lose the first word. Change the control initial to use clocks instead of# timing statements:


task wait_for_clk(int n = 1);
	for(int i = 0; i < n ; i++) @(posedge clk);
endtask
	
initial 
begin
	clk = 1;
	resetn = 1;
	fifo_data = 64'haaaaaaaaaaaaaaaa;
	fifo_empty = 0;
	fifo_startofpacket = 0;
	fifo_endofpacket = 0;
	out_ready = 0;
	fifo_valid = 0;
	
# 30
		resetn = 0;
# 50
		resetn = 1;
		
	//resyncrhonise to the clock
	wait_for_clk(4);
		fifo_valid = 1;
		fifo_startofpacket = 1;
	wait_for_clk;
		fifo_data = 64'hbbbbbbbbbbbbbbbb;
		fifo_startofpacket = 0;
	wait_for_clk;
		fifo_data = 64'hcccccccccccccccc;
	wait_for_clk;
		fifo_data = 64'hbbbbbbbbbbbbbbbb;
	wait_for_clk;
		fifo_data = 64'hdddddddddddddddd;
		fifo_endofpacket = 1;
	wait_for_clk;
		fifo_endofpacket = 0;
		fifo_valid = 0;
	wait_for_clk(5);
		out_ready = 1;
	
end

Altera_Forum · ‎02-11-2016

I confirm, that your solution worked.

I am curious now, how is it possible that other testbenches with "#" statements "worked" earlier?

I just had luck and all races ended the way I expected?

matey22

Altera_Forum · ‎02-11-2016

They probably worked because the value changed much before the clock. You just got unlucky that you aligned all of your control signals just before clock edges.

Much safer to only use# for the clock, then everything else changes relative to the clock.