'artefacts' from previous builds remain in netlist (RTL) viewer

[Altera_Forum]

original post below, first, the answer I found 

 To force a completely clean build, go into the root of the project directory and delete the folders ' db ' and ' incremental_db'  There is actually a read-me in the ' incremental_db ' folder indicating that this is so The build will take a bit longer, but you will have a clean diagram in the netlist/RTL viewer I do not have time to experiment, but would suspect that going into the data base and selectiveley deleting the appropriate partition files may be a bit more elegant way to do this   A clue as to wether or not you have this issue is simply how long it takes to generate the diagram after a build _ if it is instant, then the chances are it is just showing you the old file, but if there is a clear moment where it is generating the view, then you can be sure you are getting a fresh diagram   hope this is still of use (50 odd views later!)   now, back to the original post,,,,, Hi,   I think this may be fairly well known, but would be interested to hear others experience After doing a compile in Quartus (11, sp2, VHDL) I often use the RTL viewer as a sanity check, however, this turns out to be not so reliable. Recently, was re-architecting a (fairly small) design. In particular, I removed an entity that was a container that just contained another entity (in other other words, a redundant layer in the interface). However, despite removing the file (of the container) from the project, it still appeared in the viewer.(it did all build ok) Deleting the source code of the container made no difference. In the end, I created a new project, pulling only the sources I wanted, it built fine, and now the viewer showed the architecture correctly (well as correct as it ever is! ;))  Anyone else have similar experience? is there some (less dramatic way) to force a clean build?   Thanks for reading   Pete B

[Altera_Forum]

Never had the problem. I can only assume you did something wrong with the files in your project.

[Altera_Forum]

I'm also having problems with Quartus 11 SP2 caused from previous builds, but in my case it isn't the RTL viewer, it't the actual generated image that has bugs on some internal IPs. So far I've had problems with the single clock FIFO when using registers instead of RAM, and the SGDMA writing back its descriptor at a wrong address. 

It is very hard to reproduce, and each time it is solved by entirely deleting the db and incremental_db folders. I'm also looking for a better way to do this, and ensure each build is clean. Disabling smart compile and incremental compile isn't enough.

[Altera_Forum]

Daixiwen, 

 "when I get time" I hope to look a bit more into this I'm pretty sure that some targetted deleting of the files will help (delete those associated with the ones you've changed  I was taking the issues around the RTL viewer as just being a symptom, as I was re-architecting when I noticed this, so would expect functionality to be unchanged anyway Its only when I completely deleted the entity source I was sure something was up  I havent located any sort of build log yet, but this is low on my priority right now, but am keen to look at this  on the one hand, sorry to hear you are having these troubles, but on the other hand, glad its not just me!