assigning the clock in pin planner

[Altera_Forum]

How do i know which one to assign my clock to? Can this be arbitrarily chosen or do I have to look at some schematic? (Where can I find a schematic?)

[Altera_Forum]

If the clock input will drive a PLL inside the FPGA, then choose a dedicated clock input pin associated with a PLL. The device handbook will have information about this where it talks about PLLs and clock resources. 

 Even if no PLL is involved, I'd still recommend using a dedicated clock input pin. In the Pin Planner, these special pins are shown with a clock rising edge symbol. If your design will use a lot of the global routing resources and if a particular clock's fan-outs can be restricted to a quarter of the device, then choose a pin that can drive a regional clock where the associated logic will be placed. Regional clocks (and depending on the device family certain other similar routing that is not chip wide) and their associated pins are documented in the device handbook.

[Altera_Forum]

Will any pin with a clock rising edge symbol work? Or is there a specific pin?  

 I'm looking at the Reference Manual right now (http://www.altera.com/literature/manual/rm_si_bd_2sgx90.pdf), page 17  Is U6 this dedicated pin?

[Altera_Forum]

I was referring you to the device handbook, not a board reference manual. You need to look at the device documentation.

[Altera_Forum]

Should it work if I assign clk to any pin with a rising edge? 

 The reason I'm asking is because I'm getting this error and I think I am doing the pin assignment incorrectly. The only two inputs I have are clk and reset (which is tied to VCC)  using cable "usb-blaster [usb-0]", device 1, instance 0x00. pausing target processor: not responding. resetting and trying again: failed. leaving target processor paused

[Altera_Forum]

In the schematic of the hardware you're using you can find to which pin a clock signal is connected. Hopefully it's a dedicated clock input pin.  

 Assuming you're using an Altera development kit, you can find the schematic on the Altera website.

[Altera_Forum]

oogway, I thought by "schematic" in your first post you meant FPGA documentation rather than board documentation. peterjheijnen's response made me realize that I overlooked the fact that you're probably using the board with the reference manual you stated, not doing your own board design. If you're using that development board, then you will of course have to make all your pin assignments in Quartus match those on that board's schematic. A development board might have jumpers that give you some choices (I didn't look at your reference manual to see whether that's the case for your clock), but your choices will be limited by that board's layout.

[Altera_Forum]

You're right- sorry about the confusion. I am using the Stratix II FPGA with the Stratix II GX Transceiver Signal Integrity board (not doing my own board design). I can't seem to find the schematic on the altera website though...

[Altera_Forum]

You could file a mySupport service request to ask for the schematic. If the board came with any Quartus projects, you could at least get a valid clock pin location from that even though it won't tell you whether the board is wired with a choice of clock sources.

[Altera_Forum]

oogway, 

 On page 9-2 of the manual you referred to earlier, you will see a diagram of the clock circuitry. Also in that manual it states that the board schematics are available in the installed folders on your machine at <install path>\SIIGX_SI_Kit-v1.0.0\Docs\BoardDesignFiles.  Doesn't the kit come with any sample projects?

[Altera_Forum]

Thanks everyone. Yes, the schematic was included with the documentation at \SIIGX_SI_Kit-v1.0.0\Docs\BoardDesignFiles. I assigned the clock pin correctly and now it's working.