avalonMM_master_dynamic

Altera_Forum · ‎11-15-2008

Hi,

Where can I find the module definitions of "avalonMM_master_dynamic" and "avalonMM_slave_regfile" to synthesize the design.

Thanks a lot,

Sasi

avalonMM_master_dynamic# (.ram_id(3),

.words(64),

.width(11),

.addr_width(6),

.a_reset_active(0),

.s_reset_active(0),

.enable_active(1),

.clock_edge(1),

.no_of_avalonMM_master_dynamic_rwport(1)) dct_rsc_avalonMM_master_dynamic (

.waitrequest(dct_rsc_waitrequest),

.write(dct_rsc_write),

.read(dct_rsc_read),

.readdata(dct_rsc_readdata),

.writedata(dct_rsc_writedata),

.address(dct_rsc_address),

.offset_writedata(dct_rsc_offset_writedata),

.offset_write(dct_rsc_offset_write),

.offset_chipselect(dct_rsc_offset_chipselect),

.offset_readdata(dct_rsc_offset_readdata),

.data_in(dct_rsc_avalonMM_master_dynamic_data_in),

.addr(dct_rsc_avalonMM_master_dynamic_addr),

.we(dct_rsc_avalonMM_master_dynamic_we),

.data_out(dct_rsc_avalonMM_master_dynamic_data_out),

.clk(gls_clk),

.a_rst(gls_reset_n),

.s_rst(1'b1),

.en(dct_rsc_avalonMM_master_dynamic_en),

.rd(1'b0),

.cs(dct_rsc_avalonMM_master_dynamic_cs),

.waitreq_n(dct_rsc_avalonMM_master_dynamic_waitreq_n)

);

avalonMM_slave_regfile# (.words(64),

.width(9),

.addr_width(6),

.a_reset_active(0),

.s_reset_active(0),

.enable_active(1),

.clock_edge(1),

.no_of_avalonMM_slave_regfile_rport(1),

.no_of_avalonMM_slave_regfile_wport(1)) input_rsc_avalonMM_slave_regfile (

.chipselect(input_rsc_chipselect),

.read(input_rsc_read),

.write(input_rsc_write),

.readdata(input_rsc_readdata),

.writedata(input_rsc_writedata),

.address(input_rsc_address),

.data_in(9'bX),

.addr_rd(input_rsc_avalonMM_slave_regfile_addr_rd),

.addr_wr(6'b0),

.we(1'bX),

.data_out(input_rsc_avalonMM_slave_regfile_data_out),

.valid(input_rsc_avalonMM_slave_regfile_valid),

.clk(gls_clk),

.a_rst(gls_reset_n),

.s_rst(1'b1),

.en(input_rsc_avalonMM_slave_regfile_en)

);