[beginner] Where is display and delay instructions

[Altera_Forum]

Hello, 

 When I try to compile the code like that:  module hello_world ; initial begin $display ("Hello World "); # 15 $display ("Hello World again "); end endmodule   I get such error:  Error: Run Analysis and Synthesis (quartus_map) with revision "tut" for --rev option before running Compiler Database Interface (quartus_cdb)  I found the post similar to mine: http://www.alteraforum.com/forum/showthread.php?t=2059   does that mean, that Quartus doen't support $display and delay instructions ?   Thank you.

[Altera_Forum]

As far as I know, those two things aren't synthesizable anywhere, and are purely abstractions used in simulation. Verilog is hardware, and there is no display on your hardware until you build it, and there is no sense of time until you've built it. You may want to look at Nios II, as putting a soft processor(and a display peripheral) might be more what you're looking for.

[Altera_Forum]

--- Quote Start ---  As far as I know, those two things aren't synthesizable anywhere, and are purely abstractions used in simulation. Verilog is hardware, and there is no display on your hardware until you build it, and there is no sense of time until you've built it  --- Quote End ---    Do you mean, that there is some subsets of Verilog language - for example one subset (name it Synthesizable) is devoted to hardware synthesis, another subset (name it Behavior) is for modeling ?  I've been reading the book - "The Verilog Hardware Description Language", Fifth Edition Donald E. Thomas, Philip R. Moorby. And the code with $monitor and delay instructions is from that book. It suggests an idea to me, that I simply do not understand how to use QuartusII as modeling tool. I don't mean (a Modeling with waveform files), I mean $monitor and delay instruction and so on.  For example ModelSim (Mentor Graphics) could compile the upper code.

[Altera_Forum]

--- Quote Start ---  Do you mean, that there is some subsets of Verilog language - for example one subset (name it Synthesizable) is devoted to hardware synthesis, another subset (name it Behavior) is for modeling ?    --- Quote End ---    Yes, Only a subset of the verilog language is synthesizable. The higher level functions like $display and $monitor were really meant as aids to debugging the code   Usually you have a top level testbench that is not synthesizable that you that you tell quartus it is not the TOP of your design.  If you have have non-synthesizable debug $displays in your synthesizable code, you tell quartus to ignore these with pragma's //synthesis translate_off and //synthesis translate_on    --- Quote Start ---  For example ModelSim (Mentor Graphics) could compile the upper code.  --- Quote End ---    Yes. All the simulators will support the non-synthesizable constructs $display, $montitor, etc.  Pete